Lab1 : CPU sim Lab2 : Memory Extended Chips Using Proteus Simulator

1. Lab1 : CPU sim Lab2 :Memory Extended Chips Using Proteus Simulator

2. Lab 1: CPU Sim Objectives : 1 - To create a new machine on CPU Sim with a given set of specifications in a correct way 2- To create an instruction set on a simulated machine on CPU Sim in a correct way 3- To write an assembly language program using a given instruction set on a given machine on CPU Sim in a correct way

3. The main points should be revised for Lab • - A program consist of some instructions , each instruction consist of some microinstructions which is the atomic operation of a CPU. • - instruction is executed in two cycles : • (Fetch cycle ) and ( execute cycle) • Fetch cycle : fetch instruction from memory to instruction register . • Execute cycle : execute the instruction in IR .

4. Mem MAR PC Fetch cycle MBR IR C.U

5. Fetch Microinstructions : T1 - MAR IR (Address field) T2 - MDR (Memory) T3 - IR (MDR) T4 - PC PC + 1 T5 - decode – ir

6. Execute Cycle example LOAD microinstructions : MAR IR (Address field) MDR (Memory) ACC (MDR) LOAD Address field Mem MAR MBR ACC

7. 1. construct Hardware modules :

8. 2. set registers and main memory

9. 3. setting the microinstructions required

10. 4. design the microinstruction that transfer data between registers 5. Design the microinstruction that transfer data between registers and memory

11. 6. Design the microinstruction that increment the PC with 2 because memory is byte addressable 7. Design the microinstruction that decode the IR registers

12. 8. Design fetch sequence

13. 9. Design jmpz instruction: jump if last Arithmetic operation is zero

14. 10. Design the microinstructions of Jmpz

15. Lab2: Memory Extended Chips Using Proteus Simulator Objectives: - learn how to use Proteus simulation to simulate memory using chip 7489 Tools: - Proteus version 7.4 - Memory chips 16 X 4 bit “No 7489” - 7 SEG display

16. 1. Fetch 7489 memory chips from pick devices

17. 2. The basic memory chip connection