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Group M1 - Enigma Machine. Design Manager: Prateek Goenka Adithya Attawar (M1-1) Shilpi Chakrabarti (M1-2) Zavo Gabriel (M1-3) Mike Sokolsky (M1-4). Milestone #3 - 2/6/06 Size Estimation Floorplanning. Status Update. Completed: Design Chosen Initial Architecture
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Group M1 - Enigma Machine Design Manager: Prateek Goenka Adithya Attawar (M1-1) Shilpi Chakrabarti (M1-2) Zavo Gabriel (M1-3) Mike Sokolsky (M1-4) Milestone #3 - 2/6/06 Size Estimation Floorplanning
Status Update • Completed: • Design Chosen • Initial Architecture • Behavioral Verilog and C Simulation • Floorplan, Size Estimation, Transistor Count • In Progress • Gate-Level Verilog Design (75%) • To Do: • Choose and insert addition module(s) • Schematic • Layout • DRC/LVS • Testing
Design Decisions • Character-Based Cycle • “New Character” input pin, allows the chip to process both individual events and a continuous stream of data. • Separate Wheel and Reflector ROM • 1-bit less for addressing, removes one clock cycle from encryption • Final Architecture based on Modules • Allows for expansion (more on this later) • Control FSM designed with flexibility in mind, with several open states
Design Decisions (cont) • Operation time varies, 17 cycles for a typical 3-rotor machine. • 1 cycle load • 1 cycle steckerboard swap • 6 cycles for 2 wheels • 1 cycle for reflector • 6 cycles for 2 wheels • 1 cycle steckerboard swap • 1 cycle output • Achieve variable time through two hierarchical FSM’s, one for operation and one specifically for the wheels.
Critical Path • Reverse wheel offset lookup • Path: • Through Adder, Divider, 3 MUXs, and ROM (Large fan-in NAND, n-pass driving long signal line) • Speed estimates are waiting for final Verilog • Given the small width of the datapath, 500Mhz should be a reasonable goal for external clock speed. • Since this is by far the longest path, and since the FSM is already providing variable clocking for different parts of the circuit, it may be possible to optimize and clock the rest of the logic cycles at a much faster rate.
Clocking Issues • Design requires complex control over clock signals to different modules. • Different modules need different clocks • Also depends on state, for instance: • Wheel module, during Set phase, is clocked at the global clock rate, however during character operations it is clocked only once per encode cycle. • FSM includes clock modulators for various components that run at different speeds.
Updated Transistor Count • Transistor Count: • Muxes = 550 • RAM = 1150 • ROM = 4700 • Adders/Dividers = 450 • Registers = 800 • Counters = 1250 • FSM = 300 • Total: 9200
Block Sizes (estimates) • Adder % 26: 3500 um^2 • RAM: 10000 um^2 • ROM: 30000 um^2 • Counters : 6000 um^2 • Control/FSM: 3000 um^2 • Registers: 2500 um^2 • Total: 55,000 um^2
Floor Plan Counter &Wheel Reg. 5-bit Adder + 5-bit %26 RAM ROM FSM & Data Reg.
Metal Layers • Standard Usage: • Metal 1 • Gate connections, V++, Gnd • Metal 2 • Inter-gate connections, local routing • Metal 3 • Global routing, horizontal • Metal 4
Main Verilog Module // Main module module enigma (charout, charin, usestek, stekset, numwheels, wheelord, wheelpos, reset, set, clk); output [4:0] charout; input [4:0] charin, input [4:0] stekset, wheelset; input [2:0] wheelord; input usestek, reset, set, clk; wire [4:0] mux0out, mux1out, mux2out, mux3out, mux4out, mux5out, cregout, nregout; wire [4:0] add0out, add1out, ram0out, rom0out, rom1out, wheelpos; wire [2:0] wheel; register5b creg( cregout, mux0out, clk); register5b nreg( nregout, mux1out, clk); register5b oreg( charout, mux2out, clk); adder5bmod26 add0( add0out, nregout, cregout); adder5bmod26 add1( add1out, 5'b01101, add0out); countunit wheels( curwheel, curwheelpos, wheelset, wheelnum, wheelpos, wheelord, reset, set, clk); fsm fsm0( mux0sel, mux1sel, mux2sel, mux3sel, mux4sel, loadcnt, ramrw, ramclk, reset, set,clk); rom234x5b rom0( rom0out, {curwheel, mux3out}); rom26x5b rom1( rom1out, cregout); ram26x5b ram0( ram0out, ramrw, mux4out, stekset, ramclk); mux5bx2 mux0( mux0out, mux0sel, charin, mux2out); mux5bx2 mux1( mux1out, mux1sel, rom0out, curwheelpos); mux5bx4 mux2( mux2out, mux2sel, ram1out, rom1out, cregout, add0out); mux5bx2 mux3( mux3out, mux3sel, add0out, add1out); mux5bx2 mux4( mux4out, mux4sel, cregout, loadcnt); endmodule
Problems & Questions • Design is too small • Planning Additional Modules • “Random” wheel motion based on state of machine • Changing steckerboard parings. • Grouping characters (block cypher) • Have the previous character(s) influence encoding/decoding *** • Public/Private Key Generation (Unmatched encryption/decryption) ****** • Increase data-path(8,12,16-bit operations?)
