ES 176/276 – Section # 2 – 09/19/2011

1. ES 176/276 – Section # 2 – 09/19/2011 Brief Overview from Section #1 MEMS = MicroElectroMechanical Systems Micron-scale devices which transduce an environmental perturbation Transduction: conversion of one form of energy to another Environmental Perturbation: ex. change in temperature, pressure, altitude, humidity, chemistry, biology

2. ES 176/276 – Section # 2 – 09/19/2011 Brief Overview from Section #1 MEMS = MicroElectroMechanical Systems Micron-scale devices which transduce an environmental perturbation Transduction: conversion of one form of energy to another Environmental Perturbation: ex. change in temperature, pressure, altitude, humidity, chemistry, biology

3. ES 176/276 – Section # 2 – 09/19/2011 Brief Overview from Section #1 MEMS = MicroElectroMechanical Systems Micron-scale devices which transduce an environmental perturbation Transduction: conversion of one form of energy to another Environmental Perturbation: ex. change in temperature, pressure, altitude, humidity, chemistry, biology

4. ES 176/276 – Section # 2 – 09/19/2011 Brief Overview from Section #1 MEMS = MicroElectroMechanical Systems Ex. Schematic representation of a multi-terminal MEMS device

5. ES 176/276 – Section # 2 – 09/19/2011 Brief Overview from Section #1 MEMS = MicroElectroMechanical Systems Micron-scale devices which transduce an environmental perturbation Transduction: conversion of one form of energy to another Environmental Perturbation: ex. change in temperature, pressure, altitude, humidity, chemistry, biology Sensor:device which performs a measurement of a specific environmental perturbation Actuator: mechanical element which performs work (cantilever, beams, membranes, etc.)

6. ES 176/276 – Section # 2 – 09/19/2011 Brief Overview from Section #1 MEMS = MicroElectroMechanical Systems – Driving Force behind MEMS commercialization? – History of integrated circuit industry (why is this important?) – Evolution of MEMS to present day – Why Silicon is so present in MEMS fabrication?

7. ES 176/276 – Section # 2 – 09/19/2011 Today’s Plan – MEMS examples: (MEMS Airbag accelerometer, Digital Micromirror Device, Capacitive RF MEMS switch) NOTE: Not the latest and greatest MEMS devices, but classic examples. Your job will be to find the latest and greatest. – Planar fabrication broad overview (how ICs are made) – ICs versus MEMS, what are new fabrication requirements? -- MEMS fabrication broad overview -- Section #3, we dive in depth, maybe even some math!

8. ES 176/276 – Section # 2 – 09/19/2011 EX.1. MEMS Airbag Accelerometer

9. ES 176/276 – Section # 2 – 09/19/2011 EX. 1. MEMS Airbag Accelerometer

10. ES 176/276 – Section # 2 – 09/19/2011 EX. 2. Digital Micromirror Device

11. ES 176/276 – Section # 2 – 09/19/2011 EX. 2. Digital Micromirror Device

12. ES 176/276 – Section # 2 – 09/19/2011 EX. 3. Capacitive RF MEMS switch

13. ES 176/276 – Section # 2 – 09/19/2011 Planar Fabrication Overview Planar fabrication (a.k.a. IC fabrication, CMOS fabrication, silicon fabrication, semiconductor processing, etc. etc.) is the process of fabricating small electronic device networks in a single piece of silicon. Developed over the last 60 years, and is one of the greatest accomplishments of the past century. Has only be further developed (greater sophistication and throughput), yet not drastically revolutionized (until this past year).

14. ES 176/276 – Section # 2 – 09/19/2011 Planar Fabrication Overview We will describe a modern CMOS process flow. In the simplest CMOS technologies, we need to realize simply NMOS and PMOS transistors for circuits like those illustrated below. Process described here requires 16 masks (through metal 2) and > 100 process steps. There are many possible variations on the process flow described here, but this is the basic

15. ES 176/276 – Section # 2 – 09/19/2011 Planar Fabrication Overview

16. ES 176/276 – Section # 2 – 09/19/2011 Planar Fabrication Overview

17. ES 176/276 – Section # 2 – 09/19/2011 Important Process Steps/Terminology (before we begin) Lithography: Process of transferring a pattern from a pre-made photomask into a photoresist layer Etching: Removal of material either by a wet chemical process (wet etching) or a gaseous/plasma process (dry etching) Deposition: Addition of material (i.e. metal, insulator, semiconductor) either by physical deposition or chemical deposition methods. Annealing/Diffusion: High temperature process to reform a material layer Oxidation: Growth of SiO2 by thermal annealing in an oxygen rich environment Planarization: Polishing of a layer in order to reduce the surface features to a flat plane Ion implantation: Exposure of a material to high energy ions which are eventually incorporated into the material lattice

18. 1- Choosing a Substrate • Substrate selection: moderately high resistivity, (100) orientation, P type. 2- Active Region Formation: • Wafer cleaning, thermal oxidation (≈ 40 nm), nitride LPCVD deposition (≈ 80 nm), photoresist spinning and baking (≈ 0.5 - 1.0 µm).

19. 2- Active Region Formation (Cont’d): • Mask #1 patterns the active areas. The nitride is dry etched.

20. 2- Active Region Formation (Cont’d): (LOCOS) • Field oxide is grown using a LOCOS process. Typically 90 min @ 1000 ˚C in H2O grows ≈ 0.5 µm.

21. 3- N and P well formation: • Mask #2 blocks a B+ implant to form the wells for the NMOS devices. Typically 1013 cm-2 @ 150-200 KeV.

22. 3- N and P well formation (Cont’d): • Mask #3 blocks a P+ implant to form the wells for the PMOS devices. Typically 1013 cm-2 @ 300+ KeV.

23. 4- Gate Formation (Cont’d): • The thin oxide over the active regions is stripped and a new gate oxide grown, typically 3 - 5 nm, which could be grown in 0.5 - 1 hrs @ 800 ˚C in O2.

24. 4- Gate Formation (Cont’d): • Polysilicon is deposited by LPCVD ( ≈ 0.5 µm). An unmasked P+ or As+ implant dopes the poly (typically 5 x 1015 cm-2).

25. 4- Gate Formation (Cont’d): • Mask #6 is used to protect the MOS gates. The poly is plasma etched using an anisotropic etch.

26. 5- Tip or Extension Formation • Mask #7 protects the PMOS devices. A P+ implant forms the LDD regions in the NMOS devices (typically 5 x 1013 cm-2 @ 50 KeV).

27. 5- Tip or Extension Formation (Cont’d) • Mask #8 protects the NMOS devices. A B+ implant forms the LDD regions in the PMOS devices (typically 5 x 1013 cm-2 @ 50 KeV).

28. 5- Tip or Extension Formation (Cont’d) • Conformal layer of SiO2 is deposited using LPCVD (typically 0.5 µm).

29. 5- Tip or Extension Formation (Cont’d) • Anisotropic etching leaves “sidewall spacers” along the edges of the poly gates.

30. 6- Source and Drain Formation: • Mask #9 protects the PMOS devices, An As+ implant forms the NMOS source and drain regions (typically 2-4 x 1015 cm-2 @ 75 KeV). • Mask #10 protects the NMOS devices, A B+ implant forms the PMOS source and drain regions (typically 1-3 x 1015 cm-2 @ 50 KeV).

31. 6- Source and Drain Formation (Cont’d): • A final high temperature anneal drives-in the junctions and repairs implant damage (typically 30 min @ 900˚C or 1 min RTA @ 1000˚C. • An unmasked oxide etch allows contacts to Si and poly regions.

32. 7- Contact and Local Interconnect Formation • Ti is deposited by sputtering (typically 100 nm).

33. 7- Contact and Local Interconnect Formation (Cont’d) • The Ti is reacted in an N2 ambient, forming TiSi2 and TiN (typically 1 min @ 600 - 700 ˚C).

34. 7- Contact and Local Interconnect Formation (Cont’d) • Mask #11 is used to etch the TiN, forming local interconnects.

35. 8- Multilevel Metal Formation: • A conformal layer of SiO2 is deposited by LPCVD (typically 1 µm). • CMP is used to planarize the wafer surface.

36. 8- Multilevel Metal Formation (Cont’d) • Mask #12 is used to define the contact holes. The SiO2 is plasma etched. • A thin TiN barrier layer is deposited by sputtering (typically a few tens of nm), followed by W CVD deposition.

37. 8- Multilevel Metal Formation (Cont’d) • CMP is used to planarize the wafer surface, completing the damascene process. • Al is deposited on the wafer by sputtering. Mask #13 is used to pattern the Al and plasma etching is used to etch it.

38. 8- Multilevel Metal Formation (Cont’d) • Intermetal dielectric and second level metal are deposited and defined in the same way as level #1. Mask #14 is used to define contact vias and Mask #15 is used to define metal 2. A final passivation layer of Si3N4 is deposited by PECVD and patterned with Mask #16. • This completes the CMOS structure.

39. ES 176/276 – Section # 2 – 09/19/2011 Integrated circuit fabrication versus MEMS fabrication – What are the fundamental differences in the following devices?

40. ES 176/276 – Section # 2 – 09/19/2011 MEMS fabrication broad overview – The requirement of free-standing and mobile elements (mechanical actuators) is beyond the abilities of IC planar fabrication – MEMS development has broken new ground in planar fabrication in order to realize free-standing and mobile elements MEMS specific fabrication: (1) Surface Micromachining (2) Bulk Micromachining

41. ES 176/276 – Section # 2 – 09/19/2011 MEMS Surface Nanomachining

42. ES 176/276 – Section # 2 – 09/19/2011 MEMS Surface Nanomachining

43. ES 176/276 – Section # 2 – 09/19/2011 MEMS Bulk Nanomachining

44. ES 176/276 – Section # 2 – 09/19/2011 MEMS Bulk Nanomachining

45. ES 176/276 – Section # 2 – 09/19/2011 Comments for next time?