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What you should know about computer architecture. Patrick Crowley. Know this much. Processor design constraints are changing Transistors are plentiful and small. Long wires are slow. Power can be as important as performance
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What you should know about computer architecture Patrick Crowley UW-CSE
Know this much • Processor design constraints are changing • Transistors are plentiful and small. Long wires are slow. • Power can be as important as performance • Architectures should accommodate tomorrow’s “media” rich applications UW-CSE
Presentation Structure • Broad visions in computer architecture • Hot topics in industry and research • UW People & Expertise UW-CSE
Broad Visions • What do we do with 1 billion transistors? • wire delays make global resources expensive, architecture is key • How do we design for tomorrow’s applications? • mobility forces power constraints on architects • media rich applications are on the way UW-CSE
IEEE Computer special theme in September 1997 Very wide, very aggressive superscalar: Yale Patt (UT Austin) Trace processors: Jim Smith, Guri Sohi (Wisconsin) Single-chip multiprocessor: Kunle Olukotun (Stanford) Raw machines, expose details of a simple replicated architecture directly to the compiler: Anant Agarwal (MIT) Simultaneous multithreading: Dean Tullsen (UCSD) Billion Transistor Processors UW-CSE
Tomorrow’s Applications • Media applications include • video encode/decode • polygon and image-based graphics • audio processing - compression/recognition/synthesis of speech, music • Many devices will be/are power sensitive • laptops • handhelds, cellphones, wearables • countless other non-traditional computing devices UW-CSE
Hot Topics in Industry • VLIW • IA64, Transmeta’s Crusoe are VLIW machines • lots of multimedia processors • SMT • Compaq’s Alpha EV-8 will be a 4 context SMT • Chip Multiprocessor • IBM’s Power4 will place 2 processors on 1 die UW-CSE
Hot Topics in Research • Superspeculation (i.e., value prediction, data speculation) • Refinement of trace caches & processors • Multimedia processing UW-CSE
UW Expertise • Jean-Loup Baer • Caches: improved replacement policies and dynamic cache line sizes • Peter Van Vleet • Wayne Wong • architectures for network interfaces • Patrick Crowley • Susan Eggers & Hank Levy • Commercial OS performance on SMT • Josh Redstone UW-CSE
Know this much • Processor design constraints are changing • Transistors are plentiful and small. Long wires are slow. • Power can be as important as performance • Architectures should accommodate tomorrow’s “media” rich applications UW-CSE