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Appendix A – Part 2: Logic Circuits

Lecture 16 and 17 – Appendix Part 2 & Ch 6 Part 1. Previous State or Output. Previous State or Output. Circuit. Flip Flops. Current State or Output. New Input. Circuit. New Input. Current State or Output. Appendix A – Part 2: Logic Circuits. Sequential Logic.

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Appendix A – Part 2: Logic Circuits

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  1. Lecture 16 and 17 – Appendix Part 2 & Ch 6 Part 1 Previous State or Output Previous State or Output Circuit Flip Flops Current State or Output New Input Circuit New Input Current State or Output Appendix A – Part 2: Logic Circuits Sequential Logic Current State or output of the device is affected by the previous states Combinatorial or Combinational Logic Current State or output of the device is only affected by the current inputs Fall 2009

  2. Previous State or Output Previous State or Output Circuit Flip Flops Current State or Output New Input Appendix A – Part 2: Logic Circuits • S and R stand for set and reset respectively • constructed from a pair of cross-coupled NOR gates • the stored bit is present on the output marked Qa • If S and R inputs are both low, maintains the Qa and Qb in constant state, • If S (Set) is pulsed high while R is held low, then the Qa output is forced high,and stays high even after S returns low; • if R (Reset) is pulsed high while S is held low, then the Qa output is forced low, and stays low even after R returns low. Fall 2009

  3. Notice how the output feeds the input Fall 2009

  4. Gated SR Latch or Flip Flop • The time at which the latch is SET or RESET is controlled by a CLOCK input • Called Gated SR Latch Fall 2009

  5. Gated SR Latch built using NAND Fall 2009

  6. Gated D Latch • Inputs S and R are derived from a single input D • Clock pulse controls when the output is triggered • Samples the D input at the time the clock is HIGH and stores that info until the next clock pulse Fall 2009

  7. Potential Problem • Thus far, the assumption has been the inputs S and R (or D) not changing while CLK is HIGH • What would happen if S, R and/or D changed ? The output would change immediately • This could be a problem • To fix this (next ppt) Fall 2009

  8. Master-Slave Flip Flop Master Slave Q Q m s D D Q D Q Q Clock Clk Q Clk Q Q Use 2 D flip flops – Master – Slave – the Slave’s clock is set to zero – therefore, if there was a change in the Master’s input, D, it wouldn’t effect the slave’s Q value – the slave holds the value (a) Circuit Clock D Q m Q = Q s (b) Timing diagram Clock’s negative edge causes change • If D changes while Master CLK is HIGH, Qm changes immediately - Qs stays the same because Slave CLK=0 • Once the CLK goes LOW, Slave FF reacts because its CLK=1 – so it thens reflects D Q D The arrow only symbolizes “positive edge” clock - the arrow with the NOT symbolizes “negative edge” clock Q (c) Graphical symbol Figure A.28.Master-slave D flip-flop. Fall 2009

  9. T Flip Flop T Flip Flops are good for counters – changes its state every clock cycle, if the input, T, is 1 • Positive-edge triggered flip flop • Since the previous state of Q was 0, it complements it to 1 Fall 2009

  10. JK Flip Flop Combines the behavior of the SR and T flip flops • First three entries are the same behavior as the SR Latch (when CLK=1) • Usually the state S=R=1 undefined – for the JK Flip Flop, for J=K=1, next state is the complement of the present state Can store data like a D Flip Flop or can tie J & K inputs together and use to build counters (like a T flip flop) Fall 2009

  11. Registers and Shift Registers A Flip Flop can store ONE bit – in being able to handle a WORD, you will need a number of flip flops (32, 64, etc) arranged in a common structure called a REGISTER. • All flip flops are synchronized by a common clock • Data written into (loaded) flip flops at the same time • Data is read from all flip flops at the same time F F F F 1 2 3 4 In Out D Q D Q D Q D Q Clock Q Q Q Q Figure A.33. A simple shift register. • Want the ability to rotate and shift the data • Clock pulse will cause the contents of F1, F2, F3 and F4 to shift right (serially) • To do a rotation, simply connect OUT to IN Fall 2009

  12. Registers and Shift Registers • Can load either serially or in parallel • When clock pulse occurs, • Serial shift takes place if Shift’/Load=0 or • if Shift’/Load=1, parallel load is performed Fall 2009

  13. Counters • 3-stage or 3-bit counter constructed using T Flip Flops • With T Flip Flips, when input T=1, the flip flop toggles – changes state for each successive clock pulse • Initially all set to 0 • When clock pulse, Q0=1, therefore Q’=0 disabling Q1 and Q1 disables Q2 (have 1,0,0) • For the 2nd clock pulse, Q0=0, therefore Q’=1, causing Q1=1 and therefore Q’=0 disabling Q2 (have 0,1,0) • For the 3rd clock pulse, Q0=1, therefore Q’=0 disabling Q2 and therefore disabling Q3 (have 1,1,0) • Etc…. 000 001 010 011 100 101 110 111 Called a Ripple Counter Fall 2009

  14. Decoders Output - Decoded message Input - Encoded message Example – encoded message 01 means 2 Fall 2009

  15. Decoders – another example Fall 2009

  16. Multiplexers Depending the “select input” combination, 1 of 4 data inputs is chosen for output Example – if “select input” 10 is realized, data input on X3 is displayed as output, Z Fall 2009

  17. Multiplexers Can also use multiplexers to implement logic functions Given this truth table, group X1,X2 being 00, 01, 10 and 11 – notice what happens with X3 • 3-input truth table can be done with a 4-input mux • 4-input truth table can be done with a 8-input mux • 5-input truth table can be done with a 16-input mux • Etc.. Fall 2009

  18. Programmable Logic Devices (PLD) All possible combinations of inputs ANDed       ••• All possible combinations of ANDed inputs ORed       Fall 2009

  19. Programmable Logic Array (PLA) Ability to program a PLD, is called a PLA Fall 2009

  20. Programmable Array Logic (PAL) For a PLA, both the AND array and OR array are programmable For a PAL, the AND array is programmable and the OR array is fixed Fall 2009

  21. Complex Programmable Logic Devices (CPLDs) CPLDs are comprised of 2 or more PALs Fall 2009

  22. Field Programmable Gate Arrays (FPGAs) PAL chips are somewhat limited in size due to the fact they have output pins for each sum-of-product circuit FPGA overcome this size limitation by using a general interconnection. General interconnection PAL Fall 2009

  23. Sequential Logic Current State or output of the device is affected by the previous states Previous State or Output Previous State or Output Circuit Flip Flops Current State or Output New Input Combinatorial or Combinational Logic Current State or output of the device is only affected by the current inputs Circuit New Input Current State or Output Recall Examples: Decoders Multiplexers Examples: Shift Registers Counters Fall 2009

  24. x = 0 ¤ z = 0 S0 S1 x = 1 ¤ z = 0 x = 1 ¤ z = 0 x = 0 ¤ z = 0 x = 0 ¤ z = 0 x = 1 ¤ z = 1 x = 1 ¤ z = 0 S3 S2 x = 0 ¤ z = 1 Figure A.47.State diagram of a mod-4 up/down counter that detects the count of 2. Sequential Circuit – State Diagram If x=0, count up, If x=1, count down Interested when 2 is realized – z=1 when reach 2, else z=0 If at 0 and x=0, count up to 1 (and z=0) If at 0 and x=1, count down to 3 (and z=0) State diagram describes the functional behavior without any reference to implementation Fall 2009

  25. x = 0 ¤ z = 0 S0 S1 x = 1 ¤ z = 0 x = 1 ¤ z = 0 x = 0 ¤ z = 0 x = 0 ¤ z = 0 x = 1 ¤ z = 1 x = 1 ¤ z = 0 S3 S2 x = 0 ¤ z = 1 Figure A.47.State diagram of a mod-4 up/down counter that detects the count of 2. Sequential Circuit – State Table Can represent the info in the state diagram in a state table Fall 2009

  26. Sequential Circuit – Equation Inputs – y2,y1,x Outputs –Y2, Y1 Fall 2009

  27. Sequential Circuit – Circuit Design D Flip Flops used to store values of the two state variables between clock pulses Output from Flip Flops is the present-state of the variables Input, D, of the Flip Flops is the next-state of the variables Fall 2009

  28. Finite State Machine Model The example we just implemented is an example of a “Finite State Machine” - is a model or abstraction of behavior composed of a finite number of states, transitions between those states, and actions Your book has another example of a Finite State Machine Fall 2009

  29. Chapter 6: Arithmetic 0 + 0 + carry-in of 0 = 0 with a carry-out of 0 0 + 1 + carry-in of 1 = 2 with a carry-out of 1 1 + 1 + carry-in of 1 = 3 with a carry-out of 1 Carry-out for Is the carry-in for Fall 2009

  30. Chapter 6: Addition/Subtraction Logic Unit n full-adders can be used to add TWO n-bit numbers – called n-bit ripple-carry adder NOTE: by adding 1 to the carry-in of the LSB, can get a 2s complement from a 1s complement Able to handle k*n bits – what if you k numbers to add (each number being n bits) Fall 2009

  31. Chapter 6: 2’s Complement • For 2’s complement, the cn carry-out bit is NOT a part of the solution – for 2’s complement, the very last bit’s carry-out COULD cause an overflow • A rule for catching overflows for 2’s complement • If the last bit’s carry-out (cn) and the next to last bit’s carry-out (cn-1) are different – an overflow will occur • Therefore you can add the following equation to the adder in catching overflows for 2’s complement If they are different, the output will be HIGH or 1 Fall 2009

  32. Chapter 6: 2’s Complement • To perform the subtraction operation, X -Y • The 2’s complement of –Y must be formed • Then –Y can be added to X Can do either addition or subtraction If Add/Sub control input is set to 0, will add Y unchanged along with carry-in, c0=0 If Add/Sub control input is set to 1, Y is complemented to become 1’s complement, and carry-in, c0=1, to become 2’s complement Fall 2009

  33. Chapter 6: Fast Adders • Recall for an adder the sum function • Recall the adder’s carry-out function • Rewrite the carry-out function as • Let • Therefore the carry-out function could be • Gi is called the generate • Pi is called the propagate • In saving delay time, all Gi’s and Pi’s can be formed in PARALLEL – in one logic gate delay Fall 2009

  34. Chapter 6: Fast Adders • In substituting ci in terms of Gi and Pi, you would get • To continue the expansion, you would get All carries can be obtained after only 3 gate delays – therefore, independent of the number-of-bits needing to be added, the n-bit addition process requires ONLY 4 gate delays Fall 2009

  35. Chapter 6: Fast Adders Consider a 4-bit adder – carries can be implemented from This carry-lookahead adder requires 3 gate delays for the carries and 4 gate delays for the sums The ripple-carry adder would have required 7 gate delays for the sums and 8 gate delays for the last carry, c4 Fall 2009

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