Column-Matching Based Mixed‑Mode BIST Technique

Column-Matching Based Mixed‑Mode BIST Technique Petr Fišer Czech Technical University Karlovo nám. 13, 121 35 Prague 2 e-mail: fiserp@fel.cvut.cz

Outline • The aims of the Dissertation • Introduction to BIST • Proposed BIST design method • BOOM • Experimental results • Conclusions & future work

Ph.D. Thesis The main aim: • To develop a new BIST design method, as a better alternative to other state-of-the-art techniques, like bit-flipping, bit-fixing, etc. Better alternative = • Less area overhead • More scalability

Introduction to BIST Built-in Self-Test • Enables the device to test itself Why (to) BIST? • With increasing integration density, the amount of manufacture faults is increasing • Thus, we have to test the chip • With increasing complexity of the design, it becomes impossible to test the chip externally • Thus, we HAVE TO use BIST

Introduction to BIST Rule of Tens

BIST Equipment Structure Introduction to BIST [E.C. Stroud]

BIST Equipment Structure Introduction to BIST Test Vectors [E.C. Stroud]

BIST Equipment Structure Introduction to BIST Responses [E.C. Stroud]

BIST Equipment Structure Introduction to BIST Pass/Fail [E.C. Stroud]

The objective: the TPG design Introduction to BIST [E.C. Stroud]

Introduction to BIST Two General Approaches to BIST • Test-per-scan Connect the CUT flip-flops into a scan chain Test the circuit serially • Test-per-clock Tests the circuit in parallel

Scalability Problems Aspects involved: • BISTE design time • BISTE area overhead • Duration of the BIST (number of clock cycles needed to test the circuit) • Fault coverage These cannot be satisfied at one time

What Do Designers Want? • Design the BIST equipment as fast as possible, regardless the area overhead and the fault coverage (no time to wait) • Design the BIST equipment to be as small as possible, regardless the time it takes (low power) • High fault coverage is the most important aspect, the area overhead is next. The design time is not that important (common practice)

Naive Methods • Exhaustive Testing • Generates all the 2n patterns • 100% fault coverage ensured • Extremely slow – impossible to use in practice • Pseudo-Random Testing • Apply several pseudo-random patterns to the CUT • Fast • 100% fault coverage is not achieved • ROM-based BIST • Test patterns are stored in ROM • Fast, 100% fault coverage • Big area overhead

State-of-the-art Methods • Reseeding • The pseudo-random test patterns are generated by LFSR • More LFSR seeds are applied • Weighted Pattern BIST • Change the probability of occurrence of 1s and 0s in the PR sequence • Bit-Fixing, Bit-Flipping, Row-matching • Modify the PR patterns by additional logic

Proposed Mixed-Mode BIST Combination of pseudo-random and deterministic BIST Novel approach: the two phases are separated Pseudo-random patterns are applied first Then deterministic patterns are applied

Proposed Mixed-Mode BIST Combination of pseudo-random and deterministic BIST Novel approach: the two phases are separated Pseudo-random patterns are applied first Then deterministic patterns are applied PR patterns 0

Proposed Mixed-Mode BIST Combination of pseudo-random and deterministic BIST Novel approach: the two phases are separated Pseudo-random patterns are applied first Then deterministic patterns are applied PR patterns 1

Proposed Mixed-Mode BIST Combination of pseudo-random and deterministic BIST Novel approach: the two phases are separated Pseudo-random patterns are applied first Then deterministic patterns are applied Det. patterns 1

Column-Matching Newly proposed algorithm to synthesize the Decoder logic Deterministic BIST: • LFSR produces pseudo-random code words(C-matrix) • These are then transformed into deterministic tests computed by ATPG(T-matrix)

Column-Matching Basic Principle • Try to reorder test patterns, so that most of the Decoder outputs will be implemented as wires – a Match • This will be accomplished when two particular columns of the LFSR and test matrices will be equal • Combinational logic – the order is insignificant • Unmatched outputs have to by synthesized by a Boolean minimizer => BOOM

Column-Matching Example y0 = x4’ + x1 y1 = x3’ y2 = x2 x3’ + x2’ x4’ y3 = x0’ y4 = x4

Mixed-Mode CM • Simulate first n LFSR patterns • Determine undetected faults • Compute a test for them (ATPG) • Design a decoder generating vectors for this test and following LFSR patterns

Mixed-Mode CM ColumnMatching

Mixed-Mode CM Decoder Switch

Output Decoder Design Recall: “Unmatched outputs have to by synthesized by a Boolean minimizer => BOOM” Why BOOM? • Output decoder = multiple-output function having many inputs and outputs • Many = thousands • Available tools couldn’t handle such functions

BOOM • Heuristic two-level multi-output Boolean minimizer • Very fast, low memory demands • Efficient especially for functions having a large number of both input and output variables (up to thousands) • Advantageous for weakly specified functions (only few terms defined) • Novel approach to implicant generation (see CD-Search)

BOOM Main Phases: • CD-Search • Implicant Expansion • Implicant Reduction • CP Solution • Output reduction

CD-Search • Most innovative part • Implicants are generated top-down:by reducing the universal hypercube • We add literals to a term, until it becomes an implicant • Based on a frequency of occurrence inon-set

BOOM - IE Implicant Expansion The implicants from CD-search are expanded into PIs

BOOM - IR Implicant Reduction Reduces PIs into group implicants

BOOM - CP Covering problem solution Selects an irredundant set of implicants covering the on-set Greedy heuristic is used

Iterative minimization The result quality is improved by repeating the minimization and collecting implicants Several speed-up techniques used (buffers)

BOOM Experiments MCNC benchmarks, comparison with ESPRESSO • 139 benchmarks solved • 67 (48.2%) solved by BOOM in a shorter time • for 52 (37.4%) BOOM gave the same result • 30 (57.7%) of these equal results were reached faster

BOOM Experiments Very large problems. Espresso unusable Just two examples: • 200 inputs, 200 defined terms: in 0.06 s • 1000 inputs, 1000 defined terms: in 4 s

And the Most Important Experiments Output decoder design 37 output decoders • for 37 (100%) BOOM gave (sometimes much) better result • 27 (73%) solved in (a sometimes much) shorter time • 5 couldn’t be solved by Espresso at all

And the Most Important Experiments Output decoder design (some of them)

Scalability Once More Four important BIST aspects: • BISTE design time • Fault coverage • BISTE area overhead • BIST run length Cannot be satisfied at one time! Every designer wants something else => need for Scalability

Scalability Once More Four important BIST aspects: • BISTE design time • Fault coverage – given by ATPG • BISTE area overhead • BIST run length

Scalability Once More Four important BIST aspects We can freely adjust the lengths of the phases

CM Experimental Results Comparison with state-of-the-art methods. Equal test lengths, the area overhead is compared Compared with: • Bit-Fixing[N.A. Touba, E.J. McCluskey: Bit-Fixing in Pseudorandom Sequences for Scan BIST, IEEE Transactions on CAD, Vol. 20, No. 4, April 2001, pp. 545-555] • Weighted-pattern BIST[S. Wang: Low Hardware Overhead Scan Based 3-Weight Weighted Random BIST. Proc. 2001 IEEE International Test Conference] • Row Matching[M. Chatterjee, D.K. Pradhan: A BIST Pattern Generator Design for Near-Perfect Fault Coverage, IEEE Transactions on Computers, vol. 52, no. 12, December 2003, pp. 1543-1558] CM always better CM better in 71% CM better in 60%

CM Experimental Results Hard-to-test (and “big”) benchmarks

Conclusions & Contributions • The Column-Matching principle proposed • Influence of the lengths of the phases is studied • Very scalable, many design parameters freely adjustable • The results obtained by CM are mostly better (wrt. the area overhead) than those obtained by state-of-the-art methods • The method should serve as a basic guideline how to design more complex BIST designs, i.e., the multiple‑scan chain based BIST, the STUMPS architecture, etc. • It can be very advantageously used to test SoCs, since the LFSR may be reused for more cores.

Further Work • Use of different PRPGs instead of a LFSR (cellular automata) • Scaling the PRPG size • Combination with other methods (reseeding, weighted pattern testing) • Decomposition of the CUT • More intense incorporation of BOOM into CM

Further Work • Use of different PRPGs instead of a LFSR (cellular automata) • Scaling the PRPG size • Combination with other methods (reseeding,weighted pattern testing) • Decomposition of the CUT • More intense incorporation of BOOM into CM

BOOM Conclusions • Novel Boolean minimizer proposed • Different approach to implicant generation • Fast for functions with many inputs and outputs • Outperforms Espresso in most cases • Essential for CM Output Decoder synthesis

Further Work • FC-Min (good for many outputs) • BOOM-II (combination of BOOM and FC-Min) • Decomposition (single-level partitioning) • Output grouping • ESOP minimization • Several minor enhancements • Multiple-valued minimization • ???

Publications BOOM • 8 international conference publications • 1 journal publication • 1 research report • 4 citations Extensions of BOOM • 5 international conference publications Column-Matching • 9 international conference publications • 1 journal publication Other • 8 international conference publications

Column-Matching Based Mixed‑Mode BIST Technique