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Configurations and Considerations for DDR Memory

Configurations and Considerations for DDR Memory. Bill Gervasi Chairman, JEDEC Memory Parametrics. Agenda. DDR Market Takes Off! DDR Configurations The JEDEC Standards Process DIMMs & SO-DIMMs Making the Most of DDR Technology Previews of Coming Attractions. A Look at the DDR Market.

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Configurations and Considerations for DDR Memory

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  1. Configurations and Considerations for DDR Memory Bill Gervasi Chairman, JEDEC Memory Parametrics

  2. Agenda • DDR Market Takes Off! • DDR Configurations • The JEDEC Standards Process • DIMMs & SO-DIMMs • Making the Most of DDR Technology • Previews of Coming Attractions

  3. A Look at the DDR Market

  4. DDR Market Takes Off! Servers Workstations PC Segment 2 PC Segment 1 PC Segment 0 Mobile Graphics DDR PC133 PC133 DDR Rambus DDR PC133 PC133 DDR DDR PC133 PC100 DDR PC133 DDR 1H00 2H00 1H01 2H01

  5. DDR Configurations

  6. DDR Configurations DIMM TSOP-II TQFP SO-DIMM

  7. DDR Naming Conventions • Chips have adopted “DDR” naming • Describes data rate per pin in MHz • DDR-266A is the fastest bin: 266 MHz data rate at CL 2.0 • DDR-266B is the bulk bin: 266 MHz data rate at CL 2.5 • DDR-200 is the catchall bin: 200 MHz data rate at any CL • Modules retain the “PC” name • Describes data rate per module in MB/s • PC-2100 is the fastest bin: 2.1 GB/s on a 64 bit bus • PC-1600 is the catchall bin: 1.6 GB/s on a 64 bit bus • Small Systems specs retain “SS” name • SS-333 and SS-400 for 333 & 400 MHz data rates per pin

  8. DDR Configurations, Chips • 66 pin TSOP-II • Used for DDR-266 and DDR-200 • Inexpensive high volume plastic package • Compatible pinout for X4, X8, X16 • 64Mb to 512Mb; 1Gb in development • 100 pin TQFP • Used for SS-333 and SS-400 • Inexpensive high volume plastic package • X32 configuration • 64Mb and 128Mb

  9. DDR Configurations, Modules • Desktop & Server 184 pins, 5.25” long X64 or X72 (ECC) 64MB to 2GB Mobile & Small Form FactorÞ • 200 pins, 2.7” long • X64 or X72 (ECC) • 32MB to 512MB

  10. JEDEC Standards Process

  11. The JEDEC Standards Process • JEDEC is a non-profit standards organization • Suppliers & users and even competitors • Working together to expand the market

  12. How standards get done • Any company presents a market need • Interested companies form a Task Group • “Design assumptions” from end users • TG members take assignments • TG reviews simulations, promotes results: • Rev 0.1 = Straw man proposal • Rev 0.2 = TG agreement on approach • Rev 0.3 = Passes simulation • Rev 0.5 = Passes in hardware tester • Rev 1.0 = Passes in end user hardware

  13. Task Group to Committee • Task Group regularly reports to Committee • Ballot presented to Committee for vote • Votes addressed & suggestions gathered • Reballoted to achieve consensus • JEDEC publishes the results • Full reference design specification • Application notes from design assumptions • Free module gerbers for industry use • TG reforms as needed for ECOs, upgrades

  14. Standards Process in Action:The DDR SO-DIMM

  15. DDR SO-DIMM Standardization • Initial concept by Hitachi and Transmeta • Task Group formed: ALi, AMD, AMI2, AMP, ATP, Celestica, Hitachi, Hyundai, IBM, InterWorks, Kentron, Melco, Micron, Molex, PNY, Samsung, SiQual, Toshiba, Transmeta, Via • Tasks divided: • AMP: socket definition • Hitachi: x16 chips, two bank • Samsung: x8 chips, one bank • Melco: x16 chips, one bank; x64 or x72 bus

  16. DDR SO-DIMM Sockets Layout UserConfiguration End UserAccess Height

  17. DDR SO-DIMM Assumptions Flexible model accounts for real system layouts SeriesTermination ParallelTermination Data Memory Controller Address& Control SO-DIMM 1 SO-DIMM 0 Data LCRS LRSD0 LD1RT LD0D1 System LCRS LRSD0 LD0D1 LD1RT Base Assumption 60-90mm 10-15mm 10-15mm 10-15mm

  18. 255% DDR SO-DIMM Assumptions Full system model developed for each signal SO-DIMM 0 TL2 Socket SDRAM TL1 225% Memory Controller TL0 DQDQSDMCB SDRAM R/C A, 2 Banks 255% VTT LD0D1 LD1RT LRSD0 LCRS SO-DIMM 1 TL2 Socket SDRAM TL1 225% MotherboardTrace = 6010% TL0 DDR SO-DIMMTrace = 6010% SDRAM R/C A, 2 Banks

  19. DDR SO-DIMM Simulations Experimentation with layouts, termination

  20. DDR SO-DIMM Status • Task Group specification split into 4 sections • ¾ of ballots submitted, all passed in June • 4th section under vote nowFinal approval expected in September

  21. Standards Results:The JEDEC Modules

  22. DDR Unbuffered DIMM • Least expensive module • Limits number of loads supportable • Address bus hits all DDR SDRAMs • Fastest access time DDRSDRAM DDRSDRAM DDRSDRAM DDRSDRAM Data Data Address Data Data

  23. DDR Registered DIMM • Doubles density of each module orhalves number of address buses needed • Address bus latched before going to DDR SDRAMs • Access time increased by one clock DDRSDRAM DDRSDRAM DDRSDRAM DDRSDRAM Register Data Data Address Data Data

  24. When Size Matters DIMM 50% smaller SO-DIMM

  25. Raw Card #DRAMs ChipOrg BusWidth # Banks Notes A 8 X16 64 2 Highest density B 8 X8 64 1 Highest density C 4 X16 64 1 Lowest density C 5 X16 72 1 ECC support DDR SO-DIMM • Newest member of the DDR family • Four configurations, support 32MB to 512MB

  26. Butterfly SO-DIMMs • Perfect for notebook, especially thin & light! • Single access door to both SO-DIMMs • Also good for small form factor desktop PCs Motherboard SO-DIMM SOCKET CPU CPU SO-DIMM SOCKET

  27. Making the Most ofDDR Technology

  28. Serial Presence Detect (SPD) • Every DDR module contains an EEPROM • Contains parameters for the module • Speed and access time • Number and organization of chips • Special features such as fast random access • Programmed by module supplier • Systems use SPD to configure at boot time • Without SPD, systems must use the most conservative timings! SPD

  29. RelativePower Clocks ofLatency Active on PowerState* 100% 4% 12% 0 Inactive on 3 Active off 1 Inactive off 0.2% 4 * Not industry standard terms – simplified for brevity Sleep  0.4% 200 Power Management

  30. Using Power States Power (mW)

  31. Power: DDR vs SDR DDR-266 3X PC-100 1X PC-133 0.8X

  32. Previews ofComingAttractions

  33. Next: Small Packages FBGA • Smaller footprint • Lower inductance • Tighter layouts enabled

  34. Next: DDR FET Switched DIMM • Quadruples density of each module ordoubles number of DIMM slots • Address bus latched before going to DDR SDRAMs • Data bus sees a single load per slot DDRSDRAM DDRSDRAM DDRSDRAM DDRSDRAM Register FET FET FET FET Data Data Address Data Data

  35. Next: DDR II • Work well under way on DDR II • Double the speed • Lower power • Migration path from DDR I • Same controller can use DDR I and DDR II • Compatible process technologies

  36. Summary

  37. Summary • DDR explosion has begun • Configurations for every application • TSOPs and TQFPs for point to point • Unbuffered & Registered DIMMs for desktops & servers • SO-DIMMs for mobile & small desktop • JEDEC is the industry working together

  38. DDR Memory of choice for the future

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