Combinational Logic

Chapter 4 Combinational Logic

Outline: 4.1 Introduction. 4.2 Combinational Circuits. 4.3 Analysis Procedure. 4.4 Design Procedure. 4.5 Binary Adder-subtractor. 4.6 Decimal Adder. 4.7 Binary Multiplier. 4.9 Decoders. 4.10 Encoders. 4.11 Multiplexers.

4.1 Introduction Logic circuits for digit systems maybe  combinational or sequential.  A combinational circuit consists of logic gates whose outputs at any time are determend from only the presence combinations of inputs A Sequential circuits contain memory elements with the logic gates the outputs are a function of the current inputs and the state of the memory elements the outputs also depend on past inputs. (chapter 5)  2

4.2 Combinational Circuits A combinational circuits  n 2 possible combinations of input values  Combinational circuits n input m output Combinatixnal variables variables xoxic Circuit Specific functions  Adders, subtractors, comparators, decoders, encoders,  and multiplexers 4

4.3 Analysis Procedure A combinational circuit  make sure that it is combinational not sequential  No feedback path or memory elements.  derive its Boolean functions (truth table)  design verification 

Example: 6

F2= AB+AC+BC • T1= A+B+C • T2= ABC • T3= F2’. T1 • F1= T3+T2 • F1= T3+T2 • = F2’. T1+ABC • = (AB+AC+BC)’.(A+B+C) +ABC • = (A’+B’)(A’+C’)(B’+C’).(A+B+C) +ABC • = (A’B’+A’B’C’+B’C’+A’C’). (A+B+C) +ABC • = AB’C’+A’B’C+A’B’C+ABC

The truth table  8

4.4 Design Procedure The design procedure of combinational circuits  From the scpecification of the circuit determine the required number of inputs and outputs.  For each input and output variables assign a symbol  Derive the truth table  Derive the simplified Boolan functions for each output as a function of the input variables  Draw the logic diagram and verify the correctness of the design  9

Example: code conversion BCD to excess-3 code 11

The maps 12

The simplified functions  z = D'  y = CD +C'D‘ x = B'C + B‘D+BC'D' w = A+BC+BD Another i mplementation   z = D'  y = CD +C'D' = CD + (C+D)' x = B'C + B'D+BC'D‘ = B'(C+D) +B(C+D)' w = A+B(C+D) 13

The logic diagram  14

4-5 Binary Adder-Subtractor Half adder 0 + 0 = 0 ; 0 + 1 = 1 ; 1 + 0 = 1 ; 1 + 1 = 10  two input variables: x, y  two output variables: C (carry), S (sum)  truth table  S = x'y+xy‚ S=xÅy C = xy 15

Z 0 0 0 0 X 0 0 1 1 + Y + 0 + 1 + 0 + 1 C S 0 0 0 1 0 1 1 0 Z 1 1 1 1 X 0 0 1 1 + Y + 0 + 1 + 0 + 1 C S 0 1 1 0 1 0 1 1 Full-Adder • A full adder is similar to a half adder, but includes a carry-in bit from lower stages. Like the half-adder, it computes a sum bit, S and a carry bit, C. • For a carry-in (Z) of 0, it is the same as the half-adder: • For a carry- in(Z) of 1:

the arithmetic sum of three input bits Full-Adder :  three input bits  x, y: two significant bits  z: the carry bit from the previous lower significant bit  Two output bits: C, S  18

S = x'y'z+x'yz'+ xy'z'+xyz  C = xy + xz + yz S = zÅ (xÅy)  = z'(xy'+x‘y)+z(xy'+x'y)' = z‘xy'+z'x'y+z(xy+x‘y') = xy'z'+x'yz'+xyz+x'y'z C = z(xy'+x'y)+xy = xy'z+x'yz+ xy 20

Binary adder Note: n bit adder requires n full adders 21

Binary subtractor A-B = A+(2’s complement of B)  4-bit Adder-subtractor using M as mode of operation  M=0, A+B; M=1, A+B’+1  26

Overflow The storage is limited  Overfow cases : 1.Add two positive numbers and obtain a negative  number 2. Add two negative numbers and obtain a positive number  V = 0, no overflow; V = 1, overflow  Example: Note: XOR is used to detect overflow. 27

4-6 Decimal Adder Add two BCD's  9 inputs: two BCD's and one carry-in  5 outputs: one BCD and one carry-out  A truth table with 2^9 entries  the sum <= 9 + 9 + 1 = 19  binary to BCD 

BCD Adder: The truth Table 

In BCD modifications are needed if the sum > 9 Must add 6 (0110) in case:  C = 1  K = 1  Z8z4=1  Z = 1 Z  8 2 d Ification when C=1 we add 6: mo mo   C = K +Z Z + Z Z 8 4 8 2

Block diagram 

4.7 Binary Multiplier Partial products  –use AND operations with half adder. Note: A*B=1 only if A=B=1 Oherwise 0. fig. 4.15 Two-bit by two-bit binary multiplier.

4-bit by 3-bit binary multiplier  Fig. 4.16 Four-bit by three-bit binary multiplier. Digital Circuits

4-9 Decoder A decoder is a combinational circute that converts n-input lines to 2^n output lines. We use here n-to-m decoder n  a binary code of n bits = 2 distinct information n n input variables; up to 2 output lines only one output can be active (high) at any time

An implementation  Fig. 4.18 Three-to-eight-line decoder. 38 Digital Circuits

Demultiplexers  a decoder with an enable input  receive information in a single line and transmits  it in one of 2 possible output lines n Fig. 4.19 Two-to-four-line decoder with enable input

Decoder Examples • 3-to-8-Line Decoder: example: Binary-to-octal conversion. D0 = m0 = A2’A1’A0’ D1= m1 = A2’A1’A0 …etc

Expansion  two 3-to-8 decoder: a 4-to-16 deocder  Fig. 4.20 4 16 decoder constructed with two 3 x 8 decoders a 5-to-32 decoder? 

A0 A1 A2 3-8-line Decoder D0 – D7 E 3-8-line Decoder D8 – D15 A3 A4 E 2-4-line Decoder 3-8-line Decoder D16 – D23 E 3-8-line Decoder D24 – D31 E Decoder Expansion - Example 2 • Construct a 5-to-32-line decoder using four 3-8-line decoders with enable inputs and a 2-to-4-line decoder.

Combination Logic Implementation each output = a minterm  use a decoder and an external OR gate to  implement any Boolean function of n input variables A full-adder  S(x,y,z)=S(1,2,4,7)  C(x,y,z)= C(x,y,z)= S S (3,5,6,7) (3,5,6,7) Fig. 4.21 Implementation of a full adder with 1 decoder

two possible approaches using decoder  OR(minterms of F): k inputs  NOR(minterms of F'): 2 - k inputs n  In general, it is not a practical implementation 

4.10 Encoders The inverse function of decoder  a decoder z = D + D + D + D 1 3 5 7 The encoder can be implemented y = D + D + D + D 2 3 6 7 with three OR gates. x = D + D + D + D 4 5 6 7

An implementation  limitations  illegal input: e.g. D =D x1  3 6 The output = 111 (¹3 and ¹6) 

Priority Encoder resolve the ambiguity of illegal inputs  only one of the input is encoded  D has the highest priority  3 has the lowest priority D  0 X: don't-care conditions  V: valid output indicator 

■ The maps for simplifying outputs x and y fig. 4.22 Maps for a priority encoder

■ Implementation of priority x = D + D Fig. 4.23 2 3 Four-input priority encoder y= ¢ D + D D 3 1 2 V = D + D + D + D 0 1 2 3

Combinational Logic