EE5342 – Semiconductor Device Modeling and Characterization Lecture 28 April 28, 2010

1. EE5342 – Semiconductor Device Modeling and CharacterizationLecture 28April 28, 2010 Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc/

2. Introduction • Self heating of the transistor is proportional to the power dissipated. • Temperature Rise = ΔT = Rth ∙Power • The VBIC model was developed to simulate the BJT such that the device temperature tracked power dissipation in real time. • Other circuit simulators which accommodate thermal resistance are • HICUM • MEXTRAM

3. Rth Estimation for a Small Diode-isolated BJT Device VBE=0.87 V and VCE=20 V, RTH = 341 C/W

4. VBIC Model Highlights Self-heating effects included Improved Early effect modeling Quasi-saturation modeling Parasitic substrate transistor modeling Parasitic fixed (oxide) capacitance modeling An avalanche multiplication model included Base current is decoupled from collector current dt tl

5. 2-D Isotherm Plot- Lines Connecting Points of Equal Temperature 2-D Isotherm plots for a structure scaled to be the same as the P10 1X2X1 device.

6. Thermal Model of a SiGe HBT • The structure of a typical SiGe HBT (Heterojunction Bipolar Transistor) [1] • The Electrical circuit topology (Cauer network) for the thermal analogy model Oxide

7. One Dimensional Heat Flow in Silicon HEAT • A silicon structure can be sub-divided into several silicon slabs. • Each section contributes to the total Rth and Cth of the structure. If each section is of equal volume, their individual Rthand Cth should be equal in value. • To correspond to uniform heat flow, each section can be represented by a thermal resistance and half the total capacitance on each node of the resistor. SILICON Cth 2 SILICON AMBIENT Rth Cth 2

8. The Distributed Nature of the Heat Flow • The corresponding CTh /2 capacitors are aggregated at each node. • Note that the “ambient end”CTh /2 is short-circuited. • The distributed equivalent circuit analogy simulation is obtained from the following network. Rth n Cth 2n Rth n Rth n Rth n Cth n Cth n Cth n Rth = Total Thermal resistance for the silicon structure Cth= Total Thermal capacitance of the silicon structure n = number of sections A=area cp= thermal capacitance ρ=density t= thickness kp= thermal conductance

9. Comparison of Circuit Analogy to Davinci Simulation of the Heat Flow Dividing the structure into 10 sections. Considering a silicon structure of size 3.7umx2.5um x10um where i=1,2,3…n, n= number of sections Dotted line=Davinci simulation measurement Solid line = equivalent circuit simulation

10. Approximating the Distributed Circuit With a Single Pole Model • Converting the 10 element distributed model to a 1 pole model: • RTotal=Rth at ‘dc’ • ΔQTotal =(cp)(ρ)Tavg • For total heat consumption. Heat stored corresponds to charge stored for the equivalent circuit. Rth n Cth 2n Rth n Rth n Rth n Cth n Cth n Cth n

11. Comparison of Circuit Analogy to Davinci Simulation for Heat Flow

12. (cont’d) Results from equivalent circuit simulations Results from Davinci Simulation Results from device measurement Foster network Results from device measurement Cauer network Top of the tub Top of the oxide Top of the wafer

13. Circuit used for simulations

14. dt for VBIC-R1.5 model • Model: VBIC-R1.5. • “selft” flag set to 1. • No optimization done. • No external circuit connected. • Rth=5.8E+0 • Cth=96E-12

15. VBIC-R1.5 Y11 plot (standard data)

16. VBIC-R1.5 Y11 plot (standard data)

17. VBIC-R1.2 Y11 plot (optimized data) • For optimized data refer slide “Model Parameters”. • Circuit used is shown in “Circuit for Y parameters (optimized data)” slide.

18. Spreadsheet for Calculating the Rth and Cth • Calculations mentioned in the previous slides have been implemented in an Excel spreadsheet. • The Cauer to Foster network transformation is done.  • The spreadsheet takes the dimensions of different layers of the devices and gives corresponding Cauer and Foster network values. This enables the calculation of time constants which can be converted into a single pole. The characteristic times for the Foster network appear on a impulse response plot. Fig. 7. Electrical equivalent Cauer network of the HBT Fig. 8. Electrical equivalent Foster network of the HBT

19. - + 500 W 500 W vOUT 100 W vIN = 1 V P-P, t = 200 m-sec Effect of Rth on current feedback op-amp settling time

20. Current Feedback Op Amp Data (LMH6704) Switching Offset

21. LMH6550 impulse thermal characteristics • LeCroy sampling oscilloscope (1MW input mode) • Maximum averaging (10000) • Input nominally +/- 1V with 50 micro-sec period and 50% duty cycle. • Fractional Gain Error = FGE

22. vIN Rising Response vIN FGE vOUT

23. vIN Falling Response vOUT FGE vIN

24. Current Feedback Op-Amp (CFOA) with Simple Current Mirror (CM) Bias sup

25. Large-signal Output Voltage Transient Analysis for CFOA with Simple CM Biasing

26. Hypothesis: The Thermal Tail is a Linear Superposition of the Contribution from each Individual Circuit Stick • The contribution of individual transistor to the total thermal tail. • Used six stick classifications according to transistor type and functionality. i.e. Q10stk3-pnp-bf and Q11stk4-npn-cm • Enabled the self-heating effect in the stick of interest and disabled the self-heating effect of the remaining transistors. • Simulated the contribution of each individual stick. • The total thermal tail simulated is essentially the sum of the individual thermal tail contributions of each circuit stick.

27. The Hypothesis Supported

29. HeterojunctionElectrostatics Eo qfp EC,p qfn DEC EC,n EF,p EF,n EV,p EV,n DEV xp -xn 0

30. Poisson’s Equation Ex x -xn xp

31. Heterojunctionelectronics

32. Heterojunctionelectronics (cont)

33. Heterojunctionelectronics (cont)

34. Heterojunctiondepletion widths

35. References • Fujiang Lin, et al, “Extraction Of VBIC Model for SiGe HBTs Made Easy by Going Through Gummel-Poon Model”, from http://eesof.tm.agilent.com/pdf/VBIC_Model_Extraction.pdf • http://www.fht-esslingen.de/institute/iafgp/neu/VBIC/ • Avanti Star-spice User Manual, 04, 2001. • AffirmaSpectre Circuit Simulator Device Model Equations • Zweidinger, D.T.; Fox, R.M., et al, “Equivalent circuit modeling of static substrate thermal coupling using VCVS representation”, Solid-State Circuits, IEEE Journal of , Volume: 2 Issue: 9 , Sept. 2002, Page(s): 1198 -1206

36. Thermal Analogy References [1] I.Z. Mitrovic, O. Buiu, S. Hall, D.M. Bagnall and P. Ashburn “Review of SiGe HBTs on SOI”, Solid State Electronics, Sept. 2005, Vol. 49, pp. 1556-1567. [2] Masana, F. N., “A New Approach to the Dynamic Thermal Modeling of Semiconductor Packages”, Microelectron. Reliab., 41, 2001, pp. 901–912. [3] Richard C. Joy and E. S. Schlig, “Thermal Properties of Very Fast Transistors”, IEEE Trans. ED, ED-1 7. No. 8, August 1970, pp. 586-599. [4] Kevin Bastin, “Analysis and Modeling of self heating in SiGe HBTs” , Aug. 2009, Masters Thesis, UTA. [5] Rinaldi, N., “On the Modeling of the Transient Thermal Behavior of Semiconductor Devices”, IEEE Trans-ED, Volume: 48 , Issue: 12 , Dec. 2001; Pages:2796 – 2802.

37. Simulation … References • [1] E. Castro, S. Coco, A. Laudani, L. LO Nigro and G. Pollicino, “A New Tool For Bipolar Transistor Characterization Based on HICUM”, Communications to SIMAI Congress, ISSN 1827-9015, Vol. 2, 2007. • [2] K. Bastin, “Analysis And Modeling of Self Heating in Silicon Germanium Heterojunction Bipolar Transistors”, Thesis report, The University of Texas at Arlington, August 2009.

38. AICR Team at University of Texas Arlington - Electrical Engineering Current Earlier Contributors Kevin Bastin, MS AbhijitChaugule, MS Daewoo Kim, PhD AnuragLakhlani, MS Zheng Li, PhD KamalSinha, PhD 1PhD Student 2MS Student • Ronald L. Carter, Professor • W. Alan Davis, Associate Professor • Howard T. Russell, Senior Lecturer • Ardasheir Rahman1 • Ratan Pulugurta1 • Xuesong Xie1 • Arun Thomas-Karingada2 • Sharath Patil2 • Valay Shah2