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EEL 3705 / 3705L Digital Logic Design

EEL 3705 / 3705L Digital Logic Design. Spring 2007 Instructor: Dr. Michael P. Frank Lecture Module #1: Course Introduction and Lab 0 Preparation. Administrative Matters. Sign the attendance sheet being passed around… Clearly print your preferred email address

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EEL 3705 / 3705L Digital Logic Design

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  1. EEL 3705 / 3705LDigital Logic Design Spring 2007Instructor: Dr. Michael P. Frank Lecture Module #1: Course Introduction and Lab 0 Preparation M. Frank, EEL3705 Digital Logic, Spring 2007

  2. Administrative Matters • Sign the attendance sheet being passed around… • Clearly print your preferred email address • Pick up and sign a prerequisite form… • Turn it in at the end of class • Make sure you are enrolled on Blackboard • Email Dr. Frank ASAP if you aren’t! • Download the Quartus II software • Do Lab 0 prelab! Labs begin THIS WEEK! M. Frank, EEL3705 Digital Logic, Spring 2007

  3. Lecture Outline • Overview of the subject area: • What’s Digital Logic Design all about? • Overview of the course: • Syllabus, policies, procedures • Administrative matters: • Sign-in sheet, Prereq form, Blackboard • Prepare students to do this week’s mini-lab assignment (Lab #0) M. Frank, EEL3705 Digital Logic, Spring 2007

  4. What do we mean by “Digital Logic Design?” • Digital • Using discrete physical states (e.g., on/off transistor, high/low voltage) to represent information • Logic • Using the basic operations of Boole’s algebra of logic to interpret, manipulate and process information • Design • To conceive, plan, analyze and construct the structure of working systems that will meet application requirements M. Frank, EEL3705 Digital Logic, Spring 2007

  5. Applications of Digital Logic Design • All complex electronic systems today rely heavily on components whose design and operation is based (almost entirely) on digital logic principles, including: • Microprocessors and microcontrollers • The heart of the modern computer, and also embedded within all manner of other consumer and industrial electronic devices • Digital Signal Processors • Used in cellphones, cameras, networking equipment • CPLDs (Charge-Programmable Logic Devices) and FPGAs (Field-Programmable Gate Arrays) • Used for design prototyping & in a wide range of equipment • ASICs (Application-Specific Integrated Circuits) • Semi-custom LSI or VLSI chips, used in many specialized applications M. Frank, EEL3705 Digital Logic, Spring 2007

  6. The Basis of Digital Logic today:The MOSFET • Nearly all digital systems today (2007) are based on an electronic device called the MOSFET • Metal-Oxide-Semiconductor Field-Effect Transistor • This device is basically a voltage-controlled switch • Two basic types of FET: • nFET: The dominant charge carriers are electrons (negative) • Conducts low voltages well • pFET: The dominant charge carriers are holes (positive) • Conducts high voltages well gate source drain nFET icon used in schematics M. Frank, EEL3705 Digital Logic, Spring 2007

  7. Today’s Dominant Logic Style:CMOS • Most logic today is done in the CMOS (Complementary MOS) logic style • Each logic “gate” (hardware to perform a given logic operation) is built using both nFETs and pFETs • nFETs pull output low, pFETs pull it high • Uses energy mostly only when switching • To the right are a simple CMOS inverter circuit, and its logic gate icon • When input is high (1) output is low (0) and vice-versa. • This and a few other simple kinds of gates are sufficient to build any digital system! Vdd (PWR) Vin Vout Vss (GND) in out = ¬in M. Frank, EEL3705 Digital Logic, Spring 2007

  8. Electrical & Computer Engineeringand the Design of Electronic Systems • Although electrical engineering and computer engineering are considered to be different disciplines, it’s important to always remember that any complex electronic component has both: • physical/electrical characteristics, • such as power, current, inductance, capacitance, etc. • andcomputation-related characteristics, • e.g., information content, logical function, software, protocols • To successfully design working electronic systems requires multidisciplinary teams that understand and can take care of the engineering considerations on both sides! M. Frank, EEL3705 Digital Logic, Spring 2007

  9. What does a modernDigital Logic Designer do? System-levelrequirements Functional design • Design engineering, in general, involves taking abstract, system-level requirements, and translating them into ever-more concrete and specific designs for technological artifacts. • Digital Logic Design is no different. • In modern industrial practice, increasingly many of the steps of the design process have been automated. • This is true for digital functions especially. • See e.g. resources at eda.org • Today, computer-based tools do most of the “grunt work” and “heavy lifting” • But, the designer still has to understand what the tools are doing, in order to use them! Functional orbehavioralspecification Structuraldesign Schematic orstructuralspecification Logic design Gate-LevelDesign Designcompiler Circuit synthesis FPGAProgram Transistor-levelSchematics Loading Layout ConfiguredFPGA VLSI Mask Layers Fabrication Physical chip M. Frank, EEL3705 Digital Logic, Spring 2007

  10. Structured Engineering Design Process SystemRequirementsSpecification(SRS) InformalStatementof Needs System-LevelDesignSpecification(SLDS) CG&SReport System-LevelDesign RequirementsAnalysis Concept Generation & Selection Detailed Design(to component level) TestingReport TestingPlan DesignFiles DetailedDesignSpecification SimulationTesting ProductManufacture PrototypeSystem PrototypeTesting PrototypeManufacture M. Frank, EEL3705 Digital Logic, Spring 2007

  11. Design Projects in This Course • This semester, most of the lab assignments can be considered small design projects… • The lab assignments will build up towards one large design project (video calculator app) • and one large final project of your own choice. • In each project, you will go through a simplified version of the “structured engineering design process” just described… • Turing in deliverables for the different reports, • with the later projects being more complex. M. Frank, EEL3705 Digital Logic, Spring 2007

  12. Course Overview • Quickly go through syllabus posted on Blackboard M. Frank, EEL3705 Digital Logic, Spring 2007

  13. Lab Introduction &Hardware / Software Tools Lab Syllabus, General Lab Requirements, UP2 board, MAX 7k chip, FLEX 10K chip, Quartus II EDA tool M. Frank, EEL3705 Digital Logic, Spring 2007

  14. Lab Introduction • Go through lab syllabus • Go through General Lab Requirements document • Both are posted on Blackboard M. Frank, EEL3705 Digital Logic, Spring 2007

  15. Altera UP2 development board Read theUser Guidefor details • From University Program UP2 Education Kit • Includes two PLDs (prog. logic devs.): • EPF10K70 – Member of the FLEX 10K family of FPGAs • EPM7128S – Member of the MAX 7000 family of CPLDs M. Frank, EEL3705 Digital Logic, Spring 2007

  16. UP2 Board with Cable Connections  To 9V PowerSupply PS/2key-board or mousecable JTAGProgram-mingCable VGACable(tomonitor)  To PC ParallelPort FLEX FPGA MAX CPLD M. Frank, EEL3705 Digital Logic, Spring 2007

  17. UP2 Board Close-Up PWRin JTAGin PS2in VGAout FLEX Expansion Holes 7-SegmentDisplay Crystal Jumpers FLEX 10K 7-SegmentDisplay MAX Expansion Holes LED banks MAX 7000 FLEXDIPswitch FLEXPushbuttons MAXPushbuttons MAX DIP switches M. Frank, EEL3705 Digital Logic, Spring 2007

  18. Altera MAX 7000S series PLD • Full part number: EPM7128SLC84-7 • 84-pin PLCC package • Plastic J-Lead Chip Carrier • 2,500 usable gates • 128 Macrocells • 8 LABs • Logic Array Blocks Chipsocket Pins Femalepinheaders PLCC Chip Package M. Frank, EEL3705 Digital Logic, Spring 2007

  19. Altera FLEX 10K70 PLD • Full part number of our chip: EPF10K70RC240-4 • 240-pin RQFP package • poweR Quad Flat Pack • 3,744 LEs (Logic Elements) • ea. w. 4-input LUT (Look-Up Table), flip-flop, routing • 468 LABs (Logic Array Blocks) • group the LEs together into 8-bit arrays • 9 EABs (Embedded Array Blocks) • 2,048 bits each for programmable “megafunctions” • 70,000 typical gates • 118,000 max Pins RQFP Chip Package M. Frank, EEL3705 Digital Logic, Spring 2007

  20. Quartus II Logic Development Tool • Supports the devices onour development board • You can download a freeversion from Altera • University-licensed version is installed on most college machines • Extensive free documentation, tutorials, etc. can be downloaded from Altera’s website M. Frank, EEL3705 Digital Logic, Spring 2007

  21. Quartus II Built-In Tutorial • Try going through this to gain some initial familiarity with Quartus’ feature set and development flow M. Frank, EEL3705 Digital Logic, Spring 2007

  22. Lab #0 Prep - MAX 7000 Programming Example Demonstration of the Design and Programming of an Extremely Simple Example Circuit for the MAX 7000 PLD in Quartus M. Frank, EEL3705 Digital Logic, Spring 2007

  23. MAX Package Pin Assignments From MAX 7000 PLDFamily Datasheet (p.61): M. Frank, EEL3705 Digital Logic, Spring 2007

  24. That tells us what the package pins are…Now, what about the plug headers? M. Frank, EEL3705 Digital Logic, Spring 2007

  25. Mapping from header holes to package pins • From page 7 in the UP2 User Guide. M. Frank, EEL3705 Digital Logic, Spring 2007

  26. MAX UP2 Header Pin Assignments See UP2 User Guide, p. 7, table 3. 7-segment display pins in green taken from p.9, table 4 P2 VCCINT GLCRn GCLK1 GND dot2 VCCIO d2 12 13 g2 X 74 f2 P1 TDI c2 GND 14 15 73 72 11 9 7 5 3 1 83 81 79 77 75 TDO b2 16 17 71 70 X 10 8 6 4 2 84 82 80 78 76 GND a2 dot1 18 19 69 68 e2 OE1 OE2 GND g1 VCCIO 20 21 VCCIO 67 66 TMS f1 e1 22 23 65 64 VCCIO TCK d1 24 25 63 62 GND VCCIO c1 26 27 b1 61 60 GND 34 36 38 40 42 44 46 48 50 52 X a1 28 29 59 58 33 35 37 39 41 43 45 47 49 51 53 30 31 57 56 P3 GND 32 X GND 55 54 VCCIO VCCINT P4 Color key: Power Ground Not Attached Assigned Available M. Frank, EEL3705 Digital Logic, Spring 2007

  27. Seven-Segment Display Example • Want to display “HI.” on the 7-seg display. Active-low LED control:low = on, high = off. Unused output pins aretied to GND by default. So, LEDs are on by default. Can display “HI.” byturning off a1, d1, dot1,a2, b2, c2, d2, g2. Connect these pins to Vcc. Leave others alone. a1 a2 f1 b1 f2 b2 g1 g2 e1 c1 e2 c2 d1 dot1 d2 dot2 M. Frank, EEL3705 Digital Logic, Spring 2007

  28. Schematic for “HI.” example M. Frank, EEL3705 Digital Logic, Spring 2007

  29. Pin Assignment in Quartus M. Frank, EEL3705 Digital Logic, Spring 2007

  30. Photo Showing Proper Function M. Frank, EEL3705 Digital Logic, Spring 2007

  31. Administrative Matters • Sign the attendance sheet being passed around… • Clearly print your preferred email address • Pick up and sign a prerequisite form… • Turn it in at the end of class • Make sure you are enrolled on Blackboard • Email Dr. Frank ASAP if you aren’t! • Download the Quartus II software • Do Lab 0 prelab! Labs begin THIS WEEK! M. Frank, EEL3705 Digital Logic, Spring 2007

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