Lecture 10: Circuit Families

1. Lecture 10: Circuit Families

2. Outline • Pseudo-nMOS Logic • Dynamic Logic • Pass Transistor Logic 10: Circuit Families

3. Introduction • What makes a circuit fast? • I = C dV/dt -> tpd (C/I) DV • low capacitance • high current • small swing • Logical effort is proportional to C/I • pMOS are the enemy! • High capacitance for a given current • Can we take the pMOS capacitance off the input? • Various circuit families try to do this… 10: Circuit Families

4. Ratioed gates • The ratioed gate consists of an nMOS pulldown network and some pullup device called the static load. • When the pulldown network is OFF, the static load pulls the output to 1. When the pulldown network turns ON, it fights the static load. • The static load must be weak enough that the output pulls down to an acceptable 0. • Stronger static loads produce faster rising outputs, but increase VOL, degrade the noise margin, and burn more static power when the output should be 0. 10: Circuit Families

5. (a) Large resistors take much space • (b) nMOS pull the output up to VGG-Vt, • (c) depletion mode transitors with vgs=0 are always weakly on. 10: Circuit Families

6. Pseudo-nMOS • In the old days, nMOS processes had no pMOS • Instead, use pull-up transistor that is always ON • In CMOS, use a pMOS that is always ON • Ratio issue • Make pMOS about ¼ effective strength (1/2 effective width) of pulldown network 10: Circuit Families

7. For thewidths shown, the pMOS transistors produce I/3 and the nMOS networks produce 4I/3. • The logical effort for each transition is computed as the ratio of the input capacitance tothat of a complementary CMOS inverter with equal current for that transition. • For the falling transition: (4I/3 – I/3)=I compare with unit CMOS invertor (4/3)/3=4/9 • gu is three times as great because the current is 1/3 as much. • The parasitic delay is also found by counting output capacitance and comparing it to an inverter with equal current. 10: Circuit Families

8. Pseudo-nMOS Gates • Design for unit current on output to compare with unit inverter. • pMOS fights nMOS 10: Circuit Families

9. Pseudo-nMOS Gates • Design for unit current on output to compare with unit inverter. • pMOS fights nMOS 10: Circuit Families

10. Pseudo-nMOS Design • Ex: Design a k-input AND gate using pseudo-nMOS. Estimate the delay driving a fanout of H • G = 1 * 8/9 = 8/9 • F = GBH = 8H/9 • P = 1 + (4+8k)/9 = (8k+13)/9 • N = 2 • D = NF1/N + P = (DeMorgan: static CMOS inverters followed by a k-input pseudo-nMOS NOR) 10: Circuit Families

11. Pseudo-nMOS Power • Pseudo-nMOS draws power whenever Y = 0 • Called static power P = IDDVDD • A few mA / gate * 1M gates would be a problem • Explains why nMOS went extinct • Use pseudo-nMOS sparingly for wide NORs • Turn off pMOS when not in use 10: Circuit Families

12. Ratio Example* • The chip contains a 32 word x 48 bit ROM • Uses pseudo-nMOS decoder and bitline pullups • On average, one wordline and 24 bitlines are high • Find static power drawn by the ROM • Ion-p = 36 mA, VDD = 1.0 V • Solution: 10: Circuit Families

13. Dynamic Logic • Dynamic gates uses a clocked pMOS pullup • Two modes: precharge and evaluate 10: Circuit Families

14. As usual, the pulldown transistors’ widths are chosen to giveunit resistance. • Precharge occurs while the gate is idle and often may take place more slowly. • Therefore, the precharge transistor width is chosen for twice unit resistance. • This reduces the capacitive load on the clock and the parasitic capacitance at the expense of greater rising delays. 10: Circuit Families

15. The Foot • What if pulldown network is ON during precharge? • Use series evaluation transistor to prevent fight. 10: Circuit Families

16. Logical Effort 10: Circuit Families

17. Monotonicity • A fundamental difficulty: Dynamic gates require monotonically rising inputs during evaluation • 0 -> 0 • 0 -> 1 • 1 -> 1 • But not 1 -> 0 10: Circuit Families

18. Monotonicity Woes • But dynamic gates produce monotonically falling outputs during evaluation • Illegal for one dynamic gate to drive another! 10: Circuit Families

19. Domino Gates • Follow dynamic stage with inverting static gate • Dynamic / static pair is called domino gate • Produces monotonic outputs 10: Circuit Families

20. Domino Optimizations • Each domino gate triggers next one, like a string of dominos toppling over • Gates evaluate sequentially but precharge in parallel • Thus evaluation is more critical than precharge • HI-skewed static stages can perform logic A 8-input domino multiplexer built from two 4-input dynamic multiplexers and a HI-skew NAND gate. 10: Circuit Families

21. Dual-Rail Domino • Domino only performs noninverting functions: • AND, OR but not NAND, NOR, or XOR • Dual-rail domino solves this problem • Takes true and complementary inputs (_h and _l) • Produces true and complementary outputs 10: Circuit Families

22. Example: AND/NAND • Given A_h, A_l, B_h, B_l • Compute Y_h = AB, Y_l = AB • Pulldown networks are conduction complements 10: Circuit Families

23. Example: XOR/XNOR • Sometimes possible to share transistors 10: Circuit Families

24. Leakage • Dynamic node floats high during evaluation • Transistors are leaky (IOFF 0) • Dynamic value will leak away over time • Formerly miliseconds, now nanoseconds • Use keeper to hold dynamic node • Must be weak enough not to fight evaluation 10: Circuit Families

25. Charge Sharing • Dynamic gates suffer from charge sharing 10: Circuit Families

26. Secondary Precharge • Solution: add secondary precharge transistors • Typically need to precharge every other node • Big load capacitance CY helps as well 10: Circuit Families

27. Noise Sensitivity • Dynamic gates are very sensitive to noise • Inputs: VIH Vtn • Outputs: floating output susceptible noise • Noise sources • Capacitive crosstalk • Charge sharing • Power supply noise • Feedthrough noise • And more! 10: Circuit Families

28. Power • Domino gates have high activity factors • Output evaluates and precharges • If output probability = 0.5, a = 0.5 • Output rises and falls on half the cycles • Clocked transistors have a = 1 • Leads to very high power consumption 10: Circuit Families

29. Domino Summary • Domino logic is attractive for high-speed circuits • 1.3 – 2x faster than static CMOS • But many challenges: • Monotonicity, leakage, charge sharing, noise • Widely used in high-performance microprocessors in 1990s when speed was king • Largely displaced by static CMOS now that power is the limiter • Still used in memories for area efficiency 10: Circuit Families

30. Pass Transistor Circuits • Use pass transistors like switches to do logic • Inputs drive diffusion terminals as well as gates • CMOS + Transmission Gates: • 2-input multiplexer • Gates should be restoring 10: Circuit Families

31. LEAP • LEAn integration with Pass transistors • Get rid of pMOS transistors • Use weak pMOS feedback to pull fully high • Ratio constraint 10: Circuit Families

32. CPL • Complementary Pass-transistor Logic • Dual-rail form of pass transistor logic • Avoids need for ratioed feedback • Optional cross-coupling for rail-to-rail swing 10: Circuit Families

33. Pass Transistor Summary • Researchers investigated pass transistor logic for general purpose applications in the 1990’s • Benefits over static CMOS were small or negative • No longer generally used • However, pass transistors still have a niche in special circuits such as memories where they offer small size and the threshold drops can be managed 10: Circuit Families