APS photo gate development

1. APS photo gate development Aug 2003 LBNL Howard Wieman, Fred Bieser, Howard Matis, Marcus Oldenburg, Fabrice Retiere, Eugene Yamamoto UCI Yandong Chen, Stuart Kleinfelder

2. Outline • Why go use photo gate in CMOS APS • Model expectations • Silicon tests

3. Photo gate purpose, the problems addressed • CDS removal of fixed pattern noise and KTC reset noise • Increase signal by reducing signal spreading to adjacent pixels. The photo gate permits large geometry without adding capacitance to the sense node. P P- P+ Standard diode geometry

4. transfer gate drain photo gate 0.4 m 5 nm 1 m 1 m -2 m- x 0.1 m P epi 1.4x1015 1/cm3 8 m x = 0.4 and 0.8 m N+ 1x1020 1/cm3 (simulation quantities) Photo gate geometry • Large photo gate to collect large fraction of the charge on a single pixel, directly on the p- epi layer • Small transfer gate also directly on p- epi layer • Small drain (minimum capacitance) connected to source follower gate (sense node) reset gate photo gate reset gate transfer gate sense node drain row select gate source follower gate 20 m

5. transfer gate photo gate drain floating n well Photo gate issues in standard CMOS double poly • No double poly process – possible poor transfer between gates because of low transverse field • Floating n well between gates, a bad solution to the transfer problem with single poly • Sub-micron process may solve problem single poly

6. trans gate 1.8 V V photo gate drain 2.4 V photo gate trans gate drain V phg = 0.8 V transfer mode V phg = 2.4 V collection mode Photo gate/transfer gate operation

7. trans gate 1.8 V V photo gate drain 2.4 V photo gate trans gate drain V phg = 0.8 V transfer mode V phg = 2.4 V collection mode Photo gate/transfer gate with 800 nm separation

8. Light injection transfer gate photo gate drain 60 ns Drain current after light injection • 400 nm between photo gate and transfer gate, no floating n well • Nano amp drain current • Rapid electron transfer - complete in 60 ns

9. Light injection transfer gate photo gate drain floating n well 200 s 200 s Drain current after light injection, floating n well delay V=Q/C (very small) drain current log V drain current linear Potential before and after injection Smaller the signal the higher the effective resistance and the slower the transfer

10. Photo-gate directly to sense node drain First silicon tests Output signal for Fe55 X-ray test Issues: • Signal spreading • Reduced gain DC bias: V photo-gate 0.6 V V drain 2.4 V

11. Test of diode variation Puzzle: • No Fe55 signal • Will test with more statistics n p p p- epi