HSDSL Lab PCR CORDIC implementation on FPGA one semester project winter 2013/14

1. HSDSL LabPCRCORDIC implementation on FPGAone semester projectwinter 2013/14 Supervisor: MoniOrbach Students: Or Rotem Malachi Levi

2. Project goals • Implementing cordic algorithm in VHDL environment • Investigating different acceleration methods • Testing performance and tradeoffs

3. What is Cordic?

4. The architecture – pipeline chosentop level Compare calculation block Compare calculation block Result calculation block Result calculation block

5. The Blocks

9. Work environment • C golden model – Code Blocks • VHDL – Quartus, Model Sim • DE2 board

10. Test environment – model sim Generator real2bin DUT CORDIC Monitor- compare Output txt Cos(bin, txt) Sin(bin, txt) Angles (TXT) Golden model

11. performance test environment • Throughput – timing analysis after synthesis in model sim • Latency – timing analysis after synthesis in model sim • Resources – quartos compilation plot

12. Grant timeline synthesis Post syn simulation debugging Performers improvement Book writing

13. end

14. Appendix – cordic proof 1

15. Appendix – cordic proof