Interconnect Width Selection for Deep Submicron Designs using the Table Lookup Method

1. Interconnect Width Selection for Deep Submicron Designs using the Table Lookup Method Mandeep Bamal*, Evelyn Grossar*, Michele Stucchi and Karen Maex* IMEC , Leuven, Belgium * Also at Department of Electrical Engineering (ESAT) , Katholieke Universiteit Leuven, Belgium Mandeep.Bamal@imec.be SLIP’2004, Paris 14-15 February ,2004

2.  More Functions per area  Less Cost per function N N + 1 Metal Dielectric N : Tech. Node Silicon Introduction Backend Technology Mandeep Bamal, IMEC/ SLIP’2004, Paris

3. E-beam Optical W. Wu, R. Jonckheere, M. Stucchi, H. Struyf, Z. Tőkei, I. Vervoort, I. Vos, F. Iacopi, and K. Maex, Studies on Resistivity of Narrow Cu Interconnects, Proceedings of Advanced Metallization Conference, pp. 345-348, (San Diego, October 2002) ITRS Interconnect Delay RC trends in ITRS 2003 Mandeep Bamal, IMEC/ SLIP’2004, Paris

4. ‘Electrical equivalent sidewall damage’ S’~10nm! Technology Issues F. Iacopi, M. Stucchi, O. Richard and K. Maex, ”Electrical Equivalent Sidewall Damage in Patterned Low-k Dielectrics”,to appear in Electrochemical and Solid-State Letters, 2004. Mandeep Bamal, IMEC/ SLIP’2004, Paris

5. N N N N N N Power Delay Metal Dielectric Silicon Interconnect Exploration Let us assume that scaling continues in spite of DSM issues Hard to improve material properties Window of freedom exists for interconnect exploration Width and Height exploration for constant pitch Mandeep Bamal, IMEC/ SLIP’2004, Paris

6. Wire width Wire position Driver Load Interconnect Width Sizing • Width Sizing [Lee2000,Alpert2001,Cong2002,Jiang2001] • Decreasing the wire width progressively from source to sink.(TWS) • Multiple Width Sizing (MWS or TWS) • Uniform Width Sizing (UWS) Driver Load Problems with routing Driver Load Mandeep Bamal, IMEC/ SLIP’2004, Paris

7. 1 Driver 2 Interconnect n Interconnect Width Selection by Table Lookup Method Slew Inverter R N Adder C Type of load Buffer Length Mux. Mandeep Bamal, IMEC/ SLIP’2004, Paris

8. Variable R R Driver C1 C2 Variable slew Variable C1 Variable C2 slew Pre-Characterized Delay and Power Table Delay R C1 Power C2 4-D Lookup Table R = 0.48Rint C1 = 1/6Cint C2 = 5/6Cint + CL O’Brien/Savarino pi Model Mandeep Bamal, IMEC/ SLIP’2004, Paris

9. Exploration Methodology (Case Study-1) Mandeep Bamal, IMEC/ SLIP’2004, Paris

10. B A Driver Load Interconnect Circuit Example (2 pin net) • Assumptions • Exploration for 45 nm node • Length information obtained by using rent’s rule for a simple isotropic model of an IC (a priori length information) • Analysis done for average wire length in 2nd layer (440 um) • Driver and load both are 4x inverters • 45nm BSIM4 model card used [1] • One width per layer assumed • TAB and Total power dissipation were calculated width 100 psec 4x 4x [1] http://www-device.eecs.berkeley.edu/~ptm Mandeep Bamal, IMEC/ SLIP’2004, Paris

11. Exploration of width for optimizing delay Mandeep Bamal, IMEC/ SLIP’2004, Paris

12. Vt SI Analysis Mandeep Bamal, IMEC/ SLIP’2004, Paris

13. Power vs. Delay Normalized w.r.t. T1 Mandeep Bamal, IMEC/ SLIP’2004, Paris

14. B A Driver Load Interconnect Including Buffer Sizing 100 psec 4x 4x Normalized w.r.t. T1 and 4x Mandeep Bamal, IMEC/ SLIP’2004, Paris

15. Power-Delay Trade off’s Normalized w.r.t. T1 and 4x Mandeep Bamal, IMEC/ SLIP’2004, Paris

16. Local Interconnects ( length = 40 um) Normalized w.r.t. T1 and 4x Mandeep Bamal, IMEC/ SLIP’2004, Paris

17. Global Interconnects (length = 800 um) Normalized w.r.t. T1 and 4x Mandeep Bamal, IMEC/ SLIP’2004, Paris

18. Conclusions • Exploration can be done for interconnect dimensions • Informed choice for interconnect dimensions • Local Interconnects (very short wires…) • Not much Trade off is possible by width-only exploration • Smallest width is the best solution for constant pitch in context of power and delay optimization • Intermediate Interconnects • Significant Trade off can be made between delay and power • Global Wires • Dissipation can be traded for reducing the delay • Simultaneous buffer sizing and wire sizing is the best option • Future work • Variable pitch and height exploration • Better Signal Integrity evaluation models • Effect on area Mandeep Bamal, IMEC/ SLIP’2004, Paris

19. Thank you! questions Mandeep Bamal, IMEC/ SLIP’2004, Paris