Introduction to General Purpose Input Output (GPIO) for Zynq SoC Design

1. ECE 699: Lecture 3 General Purpose Input Output GPIO

2. Required Reading The ZYNQ Book Tutorials • Tutorial 1: First Designs on ZYNQ • Tutorial 2: Next Steps in Zynq SoC Design ZYBO Reference Manual • Section 13: Basic I/O LogiCORE IP AXI GPIO Product Specification LogiCORE IP AXI GPIO v2.0 Product Guide The ZYNQ Book • Chapter 2: The Zynq Device (“What is it?)

3. ZYBO Board Source: ZYBO Reference Manual

4. ZYBO Board Components Source: ZYBO Reference Manual

5. Source: The Zynq Book Tutorials

6. ZYBO General Purpose Input Output (GPIO) Source: ZYBO Reference Manual

7. Mapping of an Embedded SoC Hardware Architecture to Zynq Source: Xilinx White Paper: Extensible Processing Platform

8. Mapping of an Embedded SoC Hardware Architecture to Zynq Source: The Zynq Book

9. A Simplified Model of the Zynq Architecture Source: The Zynq Book

10. Source: The Zynq Book Tutorials

11. Source: The Zynq Book Tutorials

12. Source: The Zynq Book Tutorials

13. ZYBO Board Source: ZYBO Reference Manual

14. ZYBO Board Components Source: ZYBO Reference Manual

15. The Zynq Processing System Source: The Zynq Book

16. Simplified Block Diagram of the Application Processing Unit (APU) Source: The Zynq Book

17. AXI GPIO Features • Configurable single or dual GPIO channel(s) • Each channel configurable to have from 1 to 32 bits • Dynamic programming of each GPIO bit asinput or output • Individual configuration of each channel • Independent reset values for each bit of all registers • Optional interrupt request generation • AXI4-Lite interface to Processing System

18. Block Diagram of AXI GPIO enabled only when the C_INTERRUPT_PRESENT generic set to 1 IPIC – IP Interconnect interface Source: LogiCORE IP AXI GPIO: Product Specification

19. GPIO Core Source: LogiCORE IP AXI GPIO: Product Specification

20. GPIO Core Parameters Source: LogiCORE IP AXI GPIO: Product Specification

21. Setting GPIO Core Parameters in Vivado

22. Setting GPIO Core Parameters in Vivado

23. GPIO_DATA and GPIO2_DATA Registers Source: LogiCORE IP AXI GPIO: Product Specification

24. GPIO_TRI and GPIO2_TRI Registers Source: LogiCORE IP AXI GPIO: Product Specification

25. AXI GPIO System Parameters C_HIGHADDR – C_BASEADDR ≥ 0xFFF Source: LogiCORE IP AXI GPIO: Product Specification

26. Addresses of AXI GPIO Registers Source: LogiCORE IP AXI GPIO: Product Specification

27. Address Editor in Vivado

28. AXI Interconnects and Interfaces Source: The Zynq Book

29. C Program (1) /* Include Files */ #include "xparameters.h" #include "xgpio.h" #include "xstatus.h" #include "xil_printf.h" /* Definitions */ #define GPIO_DEVICE_ID XPAR_AXI_GPIO_0_DEVICE_ID /* GPIO device that LEDs are connected to */ #define LED 0x03 /* Initial LED value */ #define LED_DELAY 10000000 /* Software delay length */ #define LED_CHANNEL 1 /* GPIO port for LEDs */ #define printf xil_printf /* smaller, optimized printf */

30. C Program (2) XGpio Gpio; /* GPIO Device driver instance */ int LEDOutputExample(void) { volatile int Delay; int Status; int led = LED; /* Hold current LED value. Initialize to LED definition */ /* GPIO driver initialization */ Status = XGpio_Initialize(&Gpio, GPIO_DEVICE_ID); if (Status != XST_SUCCESS) { return XST_FAILURE; } /*Set the direction for the LEDs to output. */ XGpio_SetDataDirection(&Gpio, LED_CHANNEL, 0x00);

31. C Program (3) /* Loop forever blinking the LED. */ while (1) { /* Write output to the LEDs. */ XGpio_DiscreteWrite(&Gpio, LED_CHANNEL, led); /* Flip LEDs. */ led = ~led; /* Wait a small amount of time so that the LED blinking is visible. */ for (Delay = 0; Delay < LED_DELAY; Delay++); } return XST_SUCCESS; /* Ideally unreachable */ }

32. C Program (4) /* Main function. */ int main(void){ int Status; /* Execute the LED output. */ Status = LEDOutputExample(); if (Status != XST_SUCCESS) { xil_printf("GPIO output to the LEDs failed!\r\n"); } return 0; }

33. xparameters.h /* Definitions for driver GPIO */ #define XPAR_XGPIO_NUM_INSTANCES 1 /* Definitions for peripheral AXI_GPIO_0 */ #define XPAR_AXI_GPIO_0_BASEADDR 0x41200000 #define XPAR_AXI_GPIO_0_HIGHADDR 0x4120FFFF #define XPAR_AXI_GPIO_0_DEVICE_ID 0 #define XPAR_AXI_GPIO_0_INTERRUPT_PRESENT 0 #define XPAR_AXI_GPIO_0_IS_DUAL 0

34. Source: LogiCORE IP AXI GPIO: Product Specification

36. Constraints File

37. ZYBO General Purpose Input Output (GPIO) Source: ZYBO Reference Manual

38. entity design_1_wrapper is port ( DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_cas_n : inout STD_LOGIC; DDR_ck_n : inout STD_LOGIC; DDR_ck_p : inout STD_LOGIC; DDR_cke : inout STD_LOGIC; DDR_cs_n : inout STD_LOGIC; DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_odt : inout STD_LOGIC; DDR_ras_n : inout STD_LOGIC; DDR_reset_n : inout STD_LOGIC; DDR_we_n : inout STD_LOGIC; FIXED_IO_ddr_vrn : inout STD_LOGIC; FIXED_IO_ddr_vrp : inout STD_LOGIC; FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 ); FIXED_IO_ps_clk : inout STD_LOGIC; FIXED_IO_ps_porb : inout STD_LOGIC; FIXED_IO_ps_srstb : inout STD_LOGIC; leds_tri_o : out STD_LOGIC_VECTOR ( 3 downto 0 ) ); end design_1_wrapper;

39. design_1_i: component design_1 port map ( DDR_addr(14 downto 0) => DDR_addr(14 downto 0), DDR_ba(2 downto 0) => DDR_ba(2 downto 0), DDR_cas_n => DDR_cas_n, DDR_ck_n => DDR_ck_n, DDR_ck_p => DDR_ck_p, DDR_cke => DDR_cke, DDR_cs_n => DDR_cs_n, DDR_dm(3 downto 0) => DDR_dm(3 downto 0), DDR_dq(31 downto 0) => DDR_dq(31 downto 0), DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0), DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0), DDR_odt => DDR_odt, DDR_ras_n => DDR_ras_n, DDR_reset_n => DDR_reset_n, DDR_we_n => DDR_we_n, FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn, FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp, FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0), FIXED_IO_ps_clk => FIXED_IO_ps_clk, FIXED_IO_ps_porb => FIXED_IO_ps_porb, FIXED_IO_ps_srstb => FIXED_IO_ps_srstb, leds_tri_o(3 downto 0) => leds_tri_o(3 downto 0) );

40. ZYBO_Master.xdc (1) ##LEDs ##IO_L23P_T3_35 set_property PACKAGE_PIN M14 [get_ports {leds_tri_o[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {leds_tri_o[0]}] ##IO_L23N_T3_35 set_property PACKAGE_PIN M15 [get_ports {leds_tri_o[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {leds_tri_o[1]}] ##IO_0_35 set_property PACKAGE_PIN G14 [get_ports {leds_tri_o[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {leds_tri_o[2]}] ##IO_L3N_T0_DQS_AD1N_35 set_property PACKAGE_PIN D18 [get_ports {leds_tri_o[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {leds_tri_o[3]}]

41. ZYBO General Purpose Input Output (GPIO) Source: ZYBO Reference Manual

42. ZYBO_Master.xdc (2) ##Switches ##IO_L19N_T3_VREF_35 #set_property PACKAGE_PIN G15 [get_ports {sw[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] ##IO_L24P_T3_34 #set_property PACKAGE_PIN P15 [get_ports {sw[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] ##IO_L4N_T0_34 #set_property PACKAGE_PIN W13 [get_ports {sw[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}] ##IO_L9P_T1_DQS_34 #set_property PACKAGE_PIN T16 [get_ports {sw[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]

43. ZYBO_Master.xdc (3) ##Buttons ##IO_L20N_T3_34 #set_property PACKAGE_PIN R18 [get_ports {btn[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {btn[0]}] ##IO_L24N_T3_34 #set_property PACKAGE_PIN P16 [get_ports {btn[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {btn[1]}] ##IO_L18P_T2_34 #set_property PACKAGE_PIN V16 [get_ports {btn[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {btn[2]}] ##IO_L7P_T1_34 #set_property PACKAGE_PIN Y16 [get_ports {btn[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {btn[3]}]