Topics

1. Topics • Verilog register-transfer modeling: • basics using traffic light controller; • synthesis.

2. Verilog • Verilog was designed as an efficient simulation language. • Relatively simple, terse syntax. • Most popular HDL in use today.

3. Verilog formulas

4. Verilog constants • Bit constant: • 0, 1 • Bit vector constant: • 4’b1010

5. Some useful constructs ‘define aconst 2’b00 constant vector $monitor($time,,”a=%b, b=%b”,a,b); value monitor output #1 a=0; b=0 #2 a=1; b=0 sequence of waveforms

6. Four-valued OR function

7. Four-valued AND function

8. Time delay for output Output wire Input wires Verilog structural model Module adder(a,b,cin,sum,cout); input a, b, cin; output sum, cout; xor #2 s(sum,a,b,cin); // sum and #1 // carry out c1(x1,a,b); c2(x2,a,cin); c3(x3,b,cin); or #1 c4(cout,x1,x2,x3); endmodule

9. if (b | c) then y = 1; else y <= 0; if (b | c) then y = 1; else z = a | b; different net assigned in true, false cases y assigned value in both cases If statements

10. if (b | c) then y = ‘1’; else z = a | b; Simulation: Condition is tested based on current signal states. Only one net gets an event. Synthesis: Creates don’t-cares for y and z. Conditional assignments

11. Loop statement • A loop performs an operation over an array of signals: for (i=0; i<N; i=i+1) x[i] = a[i] & b[i];

12. always statement • always guards execution of a block of statements. • Block is always executed on the logical condition. • always @(sigval) begin .. end

13. Structure of a Verilog model • Module statement. • Declares I/O pin names. • Declarations: • inputs and outputs; • registers. • Body.

14. A synthesizable Verilog archtiecture • Declarations of pins and registers. • Definitions of constants (similar to C #define statement). • ‘define GREEN ‘2b11 • Combinational and sequential portions. • Within @always statements.

15. Verilog combinational portion always @(ctrl_state or short or long or cars) begin when HG: begin // state hwy-green highway_light = GREEN; farm_light = RED; if (cars & long) then begin ctrl_next = HY; start_timer = 1; end else begin ctrl_next - HG; start_timer = 0; end end

16. Condition on clock/reset Transfer of next state to current state Verilog sequential portion always @(posedge clock or negedge reset) if (~reset) ctrl_state <= 0; else ctrl_state <= ctrl_next; end

17. Testbench structure Unit under test (UUT) tester testbench

18. Verilog testbed organization • Module declaration. • Two components: UUT and tester. • Definition of UUT. • Definition of tester.

19. Prints signal values Test inputs Testbench tester process initial begin $monitor($time,,”a=%b”,a); #1 a=0; b=0; cin=0; #1 a=1; b=0; cin=0; #2 a=1; b=1; cin=1; end endmodule