第四章

1. 第四章 I/O Organization

2. Agenda • Single bus architecture • I/O Bus • Address lines • Data lines • Control lines • I/O addressing • Memory-mapped I/O • Isolated I/O

3. 處理器 記憶體 匯流排 I/O 裝置 n I/O 裝置 1 圖4.1 一個單一匯流排結構

4. System resources • Every I/O device will use some system resources • IRQ • Hardware interrupt • DMA Channels • For direct memory access • I/O ports (I/O addresses) • Low memory area • For communication between devices and cpu • I/O memory • Upper memory area(384K) • For device driver mapped from BIOS • For temporary data storage

5. I/O BUS • Address lines • Address the I/O devices • Data lines • Data put from device or cpu • Control lines • Read/write • When data is ready

6. I/O addressing • Memory-mapped I/O • I/O device share the same address space with memory • Isolated I/O • Special Instruction I/O • the 8086 used IN and OUT to read and write to I/O devices • A output pin of CPU differentiate the address to memory or devices

7. 位址線 資料線 匯流排 控制線 控制電路 資料與狀態 暫存器 I/O 介面 位址解碼器 輸入設備 圖4.2 輸入設備的I/O介面

8. 資料傳入 資料傳出 KIRQ SOUT SIN 狀態 DIRQ KEN 控制 DEN 7 6 5 4 3 2 1 0 圖4.3 鍵盤和顯示介面中的暫存器

9. Input Output Techniques • Program-controlled I/O • Interrupt driven I/O • DMA (Direct Memory Access)

10. Move #LINE,R0 初始化記憶體指標器。 WAITK TestBit #0,STATUS 測試SIN旗標。 Branch=0 WAITK 等待字元被輸入。 Move DATAIN,R1 讀取字元。 WAITD TestBit #1,STATUS 測試SOUT旗標。 Branch=0 WAITD 等待顯示裝置就緒。 Move R1,DATAOUT 送出字元到顯示裝置。 Move R1,(R0)+ 儲存字元並且前進指標器位置。 Compare #$0D,R1 檢查是否為Carriage Return。 Branch0 WAITK 如果不是，讀取另一個字元。 Move #$0A,DATAOUT 否則，送出換行Line Feed。 Call Process 呼叫一個子常式來處理輸入的一行資料。 Program-controlled I/O 圖4.4 程式會從鍵盤讀取一行資料，將它存到記憶體緩衝區中，並且回應到顯示裝置上

11. Interrupt driven I/O Refer to Page 4-22 圖4.9

12. 程式 1 程式 2 COMPUTE 常式 PRINT 常式 1 2 i 中斷發生於此 i + 1 M 圖4.5 中斷發生時控制權的轉換

13. Avoid infinite interrupt • Mask interrupt • Ignore interrupt until entering first instruction of interrupt service routine • Then disable interrupt in the first instruction of interrupt service routine • Enable interrupt in the last instruction of interrupt service routine

14. Multiple devices interrupt • Prioritize the devices • Eq irq0 > irq 1> irq 2 ..

15. Interrupt Vectors

16. I N T R 1 I N T R p 設備 1 設備 2 設備 p 處理器 INTA1 INTA p 優先等級仲裁電路 圖4.7 使用個別的中斷請求和確認線路的中斷優先等級實作

17. I N T R 處理器 設備 1 設備 2 設備 n INTA (a) 菊花鏈 I N T R 1 設備 設備 INTA1 處理器 I N T R p 設備 設備 INTA p 優先等級仲裁電路 (b) 優先等級群組的佈置 圖4.8 中斷優先等級方案

18. Software interrupt • System call from applications • A  interrupted by scheduler (via clock) • Context switching • Scheduler selects B • Before A’s time slice due, A requests I/O (eg. Keyboard input), A will issue system call to OS and OS will finally call I/O routine

19. IOINIT KBDINIT OSINIT 許可中斷。 設定中斷向量： 設定處理程序的狀態為Blocked。 從子常式返回。 初始化記憶體緩衝區位址指標和計數器。 Time-slice clock  SCHEDULER Software interrupt  OSSERVICES 呼叫設備驅動程式來初始化設備 KBDDATA Keyboard interrupt  IOData 檢查設備狀態。 並且許可在設備介面中的中斷。 … 從子常式返回。 如果是就緒的，那麼傳送字元。 OSSERVICES 如果字元=CR，那麼{ 設定END=1；禁止中斷} 檢查堆疊來決定被要求的操作。 IODATA 探詢設備來決定中斷的來源 呼叫適當的常式。 否則設定END=0。 SCHEDULER 呼叫適當的驅動程式。 從子常式返回。 儲存程式狀態。 選擇一個可以執行的處理程序。 如果END=1，那麼設定處理程序狀態為可執行的。 從中斷返回。 還原新處理程序被儲存的context。 推進PS和PC的新值到堆疊中。 從中斷返回。 (a) OS初始化、服務和排程程式 (b) I/O常式 (c) 鍵盤驅動程式 圖4.10 一些作業系統常式。

20. Direct Memory Access (DMA) • CPU doesn’t involve data transferring except and the beginning and the end • DMAC(DMA Controller) in charge of data transferring • CPU tells DMAC • The starting address of word to be transferred • Work counts • Direction (read or write) • When DMA is transferring data, the request AP is blocked by OS, at the same time CPU can execute other programs • When DMAC done work, it will interrupt CPU and OS will resume the blocked AP then the scheduler can schedule it

21. 31 30 1 0 狀態與控制 IRQ 完成 IE R / W 起始位址 字組計數 圖4.18 在一個DMA介面中的暫存器

22. 處理器 主記憶體 系統匯流排 磁碟/DMA 控制器 DMA 控制器 印表機 鍵盤 磁碟 磁碟 網路介面 圖4.19 在一個計算機系統中DMA控制器的使用

24. CPU involved

27. DMA mode • Burst Mode DMA – Here the DMA machine simply takes over control of the Bus • makes the data transfer at top speed • hands control back to the CPU. • This is fast, but the CPU is stopped dead for the duration ofthe transfer. • SUMMARY: • Take control of BUS. • Stop the CPU • Send all the data to Memory • Restore BUS control to CPU

28. DMA mode • Cycle Stealing • In the course of a normal program the CPU spends a lot of time executing internal CPU instructions (e.g. add ax,bx, inc bx, jnz fred) • During the execute phase of these instructions the CPU does not need control of the Bus or access to memory. In cycle stealing mode the DMA machine has the ability to “steal” bus cycles for its own data transfer, stopping the CPU. But it can also use those bus cycles that the CPU doesn’t need. • This cycle stealing approach slows down both the CPU and the DMA, but is more efficient overall. • Not an interrupt, CPU does not switch context • CPU suspended just before it accesses bus i.e. before an operand or data fetch or a data write • SUMMARY: • Take every second cycle off the CPU to use the BUS • Also take any cycle where the CPU is not using the BUS (also known as Hidden DMA)

31. BUS Arbiter • Who becomes bus master? • Centralized • distributed

32. B B S Y B R 處理器 DMA 控制器 2 DMA 控制器 1 BG1 BG2 圖4.20 一個使用菊花鏈作為匯流排仲裁的簡易佈置

33. 時間 B R BG1 BG2 B B S Y 主匯流排 處理器 DMA 控制器 2 處理器 圖4.21 圖4.20中裝置的匯流排主控權轉移期間的訊號序列 此例表示DMAC2成為bus master的時序圖

34. V cc A R B 3 A R B 2 A R B 1 A R B 0 Start-Arbitration O.C. 0 1 0 1 0 1 1 1 設備 A 的介面電路 圖4.22 一個分散式仲裁方案

35. 分散式仲裁以SCSI為例 目標檢驗 ID D B 2 D B 5 D B 6 B S Y S E L Free Arbitration Selection 圖4.42 在SCSI匯流排上的仲裁和選擇。裝置 6 贏得仲裁結果並選擇裝置 5

36. BUS timing • Synchronous bus • Includes a clock in the control lines • A fixed protocol for communication that is relative to the clock • Advantage: involves very little logic and can run very fast • Disadvantages: • Every device on the bus must run at the same clock rate • To avoid clock skew, they cannot be long if they are fast • Asynchronous • It is not clocked (using master-ready and slave-ready instead) • It can accommodate a wide range of devices • It can be lengthened without worrying about clock skew • It requires a handshaking protocol

37. Synchronous bus (ideal) 時間 匯流排時脈 定址與命令 資料 t t t 0 1 2 匯流排週期 圖4.23 一個同步匯流排上的輸入傳送時序圖

38. Synchronous bus (consider delay) 時間 匯流排時脈 被主控裝置 偵測到 t AM 定址與命令 資料 t DM 被從動裝置 偵測到 t AS 定址與命令 資料 t DS t t t 0 2 1 圖4.24 圖4.23的輸入傳送的詳細時序圖

39. Asynchronous bus 時間 定址與命令 主控裝置就緒 從動裝置就緒 資料 t t t t t t 0 1 2 3 4 5 匯流排週期 圖4.26 在輸入操作期間資料傳遞的信號交換控制

40. Asynchronous bus 時間 定址與命令 資料 主控裝置就緒 從動裝置就緒 t t t t t t 0 1 2 3 4 5 匯流排週期 圖4.27 在輸出作業期間資料傳遞的信號交換控制

41. Parallel port vs serial port • serial port • Information is transferred in or out one bit at a time • RS232 • USB • Firewire (IEEE 1394) • Serial ATA (Disk) • parallel port • data is transferred in or out in parallel • Printer port • microprocessor to communicate with peripherals • PCI • SCSI • Parallel ATA (Disk)

42. Types of Buses • Processor-Memory Bus (design specific) • Short and high speed • Only need to match the memory system • Maximize memory-to-processor bandwidth • Connects directly to the processor • Optimized for cache block transfers • I/O Bus (industry standard) • Usually is lengthy and slower • Need to match a wide range of I/O devices • Connects to the processor-memory bus or backplane bus • Backplane Bus (standard or proprietary) • Backplane: an interconnection structure within the chassis • Allow processors, memory, and I/O devices to coexist • Cost advantage: one bus for all components

43. Standard I/O interfaces 處理器 主記憶體 處理器匯流排 橋接器 PCI 匯流排 SCSI USB ISA 額外的記憶體 乙太介面 控制器 控制器 介面 SCSI 匯流排 IDE 磁碟 影像 光碟機 控制器 磁碟控制器 光碟機 磁碟 1 磁碟 2 鍵盤 遊戲 圖4.38 一部計算機使用不同介面標準的範例

44. A Computer System with One Bus: Backplane Bus Backplane Bus Processor Memory • A single bus (the backplane bus) is used for: • Processor to memory communication • Communication between I/O devices and memory • Advantages: Simple and low cost • Disadvantages: slow and the bus can become a major bottleneck • Example: IBM PC - AT I/O Devices

45. ISA bus expansion slots Buses in PC-XT and PC-AT • ISA (Industry Standard Architecture) • IBM-PC and PC-XT: 8 bits at 4.77MHz, directly connect to 8088, 2-stage bus cycle (2.38Mbyte/sec bus bandwidth) • AT bus: extension slot + 8 bit ISA • 16 bits at 8.33MHz for 80286 timer, int. contl. BIOS bus buffer CPU DRAM contrl. DMA contrl. DRAM

46. Processor Memory Bus Processor Memory Bus Adaptor Bus Adaptor Bus Adaptor I/O Bus I/O Bus I/O Bus A Two-Bus System • I/O buses tap into the processor-memory bus via bus adaptors: • Processor-memory bus: mainly for processor-memory traffic • I/O buses: provide expansion slots for I/O devices • Apple Macintosh-II • NuBus: Processor, memory, and a few selected I/O devices • SCCI Bus: the rest of the I/O devices

47. ISA bus expansion slots Buses in PC(486) • 16-bit ISA cannot support Window applications --- video data • VESA LB (local bus) -- linked to 486 local bus, 33MHZ, 32 bits DRAM 486 CPU local bus L2 cache ISA bridge bus buffer video card LAN adapter HDD contrl.

48. Processor Memory Bus Processor Memory Bus Adaptor Bus Adaptor I/O Bus Backplane Bus Bus Adaptor I/O Bus A Three-Bus System • A small number of backplane buses tap into the processor-memory bus • Processor-memory bus is only used for processor-memory traffic • I/O buses are connected to the backplane bus • Advantage: loading on the processor bus is greatly reduced

49. Buses in PC (Pentium) Pentium CPU • A three-bus system host bus PCI chipset PCI bridge Data bus L2 Cache Memory PCI bus HDD CD-ROM LAN adapter PCI/ISA bridge SCSI adapter IDE controller Video card monitor ISA bus SuperIO chip sound card Modem