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Wafer Level Packaging: recommendations for industrialization

Wafer Level Packaging: recommendations for industrialization. AIDA-2020 Annual Meeting Oxford, 3 rd of April 2019 A. Volpe / INFN Genoa. On behalf of: G. Darbo , C. Gemme , A. Lapertosa, A. Rovani – INFN Genoa P. Conci , F. Mattedi – MicroFabSolutions.

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Wafer Level Packaging: recommendations for industrialization

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  1. Wafer Level Packaging:recommendations for industrialization AIDA-2020 Annual Meeting Oxford, 3rd of April 2019 A. Volpe / INFN Genoa • On behalf of: • G. Darbo, C. Gemme, A. Lapertosa, A. Rovani – INFN Genoa • P. Conci, F. Mattedi – MicroFabSolutions A. VolpeAIDA-2020 – WP6 HV-CMOS Hybridization Oxford, 3rd April 2018

  2. Outline A. VolpeAIDA-2020 – WP6 HV-CMOS Hybridization Oxford, 3rd April 2018

  3. Introduction See: https://indico.cern.ch/event/677272/contributions/2980641/attachments/1639227/2616689/18-04 25_GD_AIDA2020.pdf INFN Genoa investigated several solutions to build capacitive coupled devices. Recently, a collaboration with MicroFabSolutions (Trento) started to overcome some technical difficulties and find new ways to industrialize capacitive/resistive coupling. • This partnership led to develop the Wafer Level Packaging (WLP), which allows to obtain larger detectors reassembling only working tiles on a full wafer. Dicing Rebuilt wafer Tiles selection Packaging A. VolpeAIDA-2020 – WP6 HV-CMOS Hybridization Oxford, 3rd April 2018

  4. WLP benefits A very accurate positioning of tiles at wafer level allows to obtain the same precision in the modules The low production yield of original wafers can be “cheated” reassembling only good tiles Any size of modules (ready to be processed) can be easily obtained from rebuilt wafers WLP is a well known technology in the industrial world Manifacturing friendly A. VolpeAIDA-2020 – WP6 HV-CMOS Hybridization Oxford, 3rd April 2018

  5. Technical requirements • The rebuilt wafers should respect some technical specifications in order to be compatible with wafer processes related to the assembly of pixel modules for modern tracking detectors: • THICKNESS: thinner tiles and wafers have a lower radiation length, being therefore more transparent to particles; • PLANARITY: maximum bowing of rebuilt wafers is required to be minimal to carry out other operations; • TILES PLACEMENT: a high accuracy in tiles alignment is required to perform wafer processes on pixel cells (tens of microns) A. VolpeAIDA-2020 – WP6 HV-CMOS Hybridization Oxford, 3rd April 2018

  6. Setup design Design and fabrication of a tool to perform wafer compression molding Optimization of pressure, temperature and cycle time The setup designed at MicroFabSolutions allows to produce 6-inch wafers A. VolpeAIDA-2020 – WP6 HV-CMOS Hybridization Oxford, 3rd April 2018

  7. Tiles positioning Microfabrication of patterned silicon wafers for tiles alignment (carrier system) Marker for tiles alignment Die Die Die Dummy chips 2x2 cm2 300 μm thickness Placing dies on support wafer + thermal release tape Thermal release tape Support wafer The tape has a high adhesive adhesion (fixing of the dies during molding) which becomes lower (debonding of the carrier system) at a defined temperature A. VolpeAIDA-2020 – WP6 HV-CMOS Hybridization Oxford, 3rd April 2018

  8. Wafer Level Molding Tiles and epoxy molding compound (EMC) opposite to foaming layer side Support wafer EMC (81 % Si) Loading phase Die Die Die Die Die Die Die Die Die Die Die Die Die Die Die Curing 130 °C 10 min Pressure + heat Support wafer Heat treatment for tape release Foaming 190 °C 1 min Support wafer Carrier system removal Peeling 20 °C A. VolpeAIDA-2020 – WP6 HV-CMOS Hybridization Oxford, 3rd April 2018

  9. Reconstructed wafer Peeling back Release tape (tiles side) After molding Final product The EMC (81% Si) and the embedded elements have very similar chemical compositions and CTE A. VolpeAIDA-2020 – WP6 HV-CMOS Hybridization Oxford, 3rd April 2018

  10. Test structures Six 6-inch wafers with different thickness and filling scheme were produced by MicroFabSolutions to find out limits of the production process and investigate the mechanical strength of the prototypes. Cross template Nitto release tape First production Mitsui release tape Second production First production Nitto release tape Full template Second production Mitsui release tape A. VolpeAIDA-2020 – WP6 HV-CMOS Hybridization Oxford, 3rd April 2018

  11. Critical issues Tape removal is a critical phase, due to the peel stress. Nitto tape was harder to remove than Mitsui tape. • Thickness 400 μm • Nitto tape The release tape plays a crucial role in the structural integrity of the wafer. A. VolpeAIDA-2020 – WP6 HV-CMOS Hybridization Oxford, 3rd April 2018

  12. Measurements High precision wafer profilemeasurements in INFN Genoa KLA P-7 mechanicalprofilometer (1 μm step) Testsoutline • Overallplanaritymeasurement in 2 directions (x/y) Y • Tiles displacementmeasurement X A. VolpeAIDA-2020 – WP6 HV-CMOS Hybridization Oxford, 3rd April 2018

  13. Results X direction I production Nitto tape → bending lines 675 μm 300 μm II production Mitsui tape → improved planarity 400 μm Z [μm] Y direction 675 μm 300 μm 300 μm thick wafer 400 μm X [mm] Y [mm] A. VolpeAIDA-2020 – WP6 HV-CMOS Hybridization Oxford, 3rd April 2018

  14. Results 8 measurements of chip-to-chip profile (1 μm precision) Tiles placement accuracycalculatedas the RMS of the distancebetweentiles Tile A Tile B Z [μm] Cross height 0.80 ± 0.05 μm X [μm] 1 μm Difference in heightbetweentiles 367 ± 50 μm (Average, 7 measur.) 12 ± 1 μm (Average, 4 measur.) Using Mitsui tape seems to haveimproved the positionigaccuracy (compatible with P&P) A. VolpeAIDA-2020 – WP6 HV-CMOS Hybridization Oxford, 3rd April 2018

  15. Conclusion • Wafers are strong enough to be handled, even the thinnerones (300 μm); • First wafer production (675 & 400 μm): • profilesshowing bending lines • source of the issue identified in the tape removal • New release tape used for 300 μm wafers (second production): • improved wafer planarity • seems to haveimprovedtiles positioning too • R&D activities carried out in contact with industry: • first step towards the industrialization of the WLP process • Products are close to meet technical specifications: • Microfab Solutions will use a more precise P&P for the nextprototypes • furthertestsneeded to confirm the validity of the procedure A. VolpeAIDA-2020 – WP6 HV-CMOS Hybridization Oxford, 3rd April 2018

  16. Thank you for your attention A. VolpeAIDA-2020 – WP6 HV-CMOS Hybridization Oxford, 3rd April 2018

  17. A. VolpeAIDA-2020 – WP6 HV-CMOS Hybridization Oxford, 3rd April 2018

  18. Backup slides A. VolpeAIDA-2020 – WP6 HV-CMOS Hybridization Oxford, 3rd April 2018

  19. Compression Molding • Detailed work flow • Vacuum pump on • Waitingthat pressure reaches 2E-4 mbar • Start heating • Applying 15000 N with mold • Curing (10 min) • Vacuum pump off • Cooling down • Removing wafer Best result with XV5791S14 Panasonic resin -“Liquid Compression Mould” with low CTE, low modulus and high Tg(170 °C) - Filler loading: 81% (Si) and max size 5 μm A. VolpeAIDA-2020 – WP6 HV-CMOS Hybridization Oxford, 3rd April 2018

  20. Applying tape A. VolpeAIDA-2020 – WP6 HV-CMOS Hybridization Oxford, 3rd April 2018

  21. Release tape function A. VolpeAIDA-2020 – WP6 HV-CMOS Hybridization Oxford, 3rd April 2018

  22. Wafer 400 μm: 3D profile Z [μm] Y [mm] X [mm] A. VolpeAIDA-2020 – WP6 HV-CMOS Hybridization Oxford, 3rd April 2018

  23. Chip-to-chip wells μm X Moldroughness mm Tiles separation 367 ± 50 μm wide 12 ± 1 μm deep Chip lenght (2 cm) A. VolpeAIDA-2020 – WP6 HV-CMOS Hybridization Oxford, 3rd April 2018

  24. Chip-to-chip (empty) wells μm μm μm μm μm μm μm μm A. VolpeAIDA-2020 – WP6 HV-CMOS Hybridization Oxford, 3rd April 2018

  25. Chip-to-chip (full) wells μm μm μm μm μm μm μm μm A. VolpeAIDA-2020 – WP6 HV-CMOS Hybridization Oxford, 3rd April 2018

  26. Future developments The tiles alignment precision may be improved introducing shifts in the tiles positioning before the molding process, to compensate for the shrinkage of the material during the curing and cooling of the compound. Total shrinkage A. VolpeAIDA-2020 – WP6 HV-CMOS Hybridization Oxford, 3rd April 2018

  27. Future developments The WLP technique may be exploited to build wafer packages piled together and interconnected through metallic vias. Three steps are required: Compression molding of a unique multilayer wafer 1 2 Etching of vias Metallization of vias 3 A. VolpeAIDA-2020 – WP6 HV-CMOS Hybridization Oxford, 3rd April 2018

  28. Future developments The WLP technique may be exploited lateral processing to build edge flip detector. To make this challenging assembly we need to use a customized Pick&Place Die Die Die Die Die Die Die Die Die Die Die Die A. VolpeAIDA-2020 – WP6 HV-CMOS Hybridization Oxford, 3rd April 2018

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