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Final Project Preparation

Final Project Preparation. Agenda. Class Evaluations Accept proposals Discuss “official” final project topic Discuss general design challenges and tools when using common final project pieces. VGA Controller FFT DDR SDRAM Reconvene in K223 for Lab 6 demonstrations .

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Final Project Preparation

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  1. Final Project Preparation

  2. Agenda • Class Evaluations • Accept proposals • Discuss “official” final project topic • Discuss general design challenges and tools when using common final project pieces. • VGA Controller • FFT • DDR SDRAM • Reconvene in K223 for Lab 6 demonstrations

  3. Project : Introduction IntroductionThis project will be heavily based on the SDR Framework that was built in Labs 4-6, but will provide additional signal processing functionality.  As before, consider the band-limited input signal which is presented at the input of the digitizer at 43.75 +/- 3 MHz.  This swath of spectrum shall be defined to be broken into 150 channels, each of which is 40kHz wide (e.g. 43.75 +- 20kHz, 43.754 +/- 20kHz,...etc.   2.75 9.25 0 (DC) 12.5MHz

  4. Project : Features Auto-channel-tuningIn this application, the FPGA will be responsible for monitoring the entire space to see if there is energy in any of the channels.  If energy in any of the channels goes above that which would be seen with just noise input, the FPGA should automatically tune to the center frequency of that (most powerful) channel and operate as in Lab 6 (I/Q to audio DAC, and to PC via. UDP data streaming) Wideband Spectrum MonitoringAlthough the UDP data streaming allows one to have a good picture of the spectrum within the channel, it is also desirable to see a broader picture of the entire digitized space (or at the very least the entire space of all channels in 40.75-46.75).  This will be visualized via a direct video feed from the FPGA.  Upon hooking a monitor to the FPGA board, the user shall be presented with a spectrum monitor in the form of an FFT magnitude plot which updates in real-time, or a “waterfall” plot.  Lots of options exist here, let one of the instructors know if you need further suggestions or definitions of appropriate ways to visualize the data.

  5. Project : Demo • DemonstrationIn automatic tuning mode, the instructor can drive arbitrary frequencies (43.75+/- 3) into the board, which should sense their presence, and automatically tune to the appropriate channel center. (with some sort of indication to the user that retuning is occuring) Then the user can listen to movement of the signal within that band via audio port, while observing streaming UDP.   • Note that the bandwidth of these channels is wider than the passband of your channel selection filter (+/- 15kHz), so the amplitude of the signal will not be flat as it moves to the channel edges... (in fact, by the time the signal has moved into the next channel, it will be attenuated by a fair amount)   • All the while, the spectrum of the entire digitized space can be visualized on the attached VGA monitor.  Updates to this display should occur frequently enough that feedback to the user seems immediate (at least a few times per second)

  6. Visualization • Live spectrum display on VGA Monitor • Option 1 : Very similar to the plot we get from the Lab 6 “collect_data” script: • On the external monitor • Contains entirety of 6MHz band of interest (more if you like) • Update at reasonable speed • Legend not required to be displayed, but must be documented

  7. Waterfall Plot (Spectrogram) Example Gives information on frequency vs. time Time on one axis, Frequency on another, Magnitude encoded as color. As simple as storing some # N previous FFT results. Pixel value = FFT Magnitude at That time and FFT #

  8. FFT for Spectrum Monitoring • To auto-tune to a presented signal based on channel strength, one needs to be able to monitor the entire 12.5MHz band for signals, with enough resolution to decide which channel to tune to • FFT bin width will be Fs/L • L = length of FFT • This same FFT can be used to provide data to the visualization engine. • FFT need not be computed continuously, rather it can be computed only at a rate sufficient to: • Update the screen quickly enough • Retune at a reasonable interval • (both of these numbers can be the same, several Hz or so)

  9. Computation of FFT • Software in Microblaze • Direct FFT computation in software based on input data. • Result can be directly used to tune • Result can be output to visualization engine • Hardware in FPGA • Logicore FFT can be used to calculate FFT in FPGA fabric. • Result can simply be read by microblaze and visualization engine.

  10. FFT Core

  11. FFT Core

  12. FFT Core

  13. FFT Core

  14. FFT -> Power • FFT Result is a complex number, to compare powers between bins and levels, we must get the magnitude of this complex number. • Mag^2 = Re*Re + Im * Im • Mag = Sqrt(Re*Re + Im * Im) • Magnitude Estimate : |V| = Max + Min/2 • Max = Max ( abs(Re), abs(Im)) • Min = Min ( abs(Re), abs(Im)) • Error avg = .71dB, always less than 1dB

  15. VGA on S3ADSP Reference Board(overview) FPGA HSYNC VSYNC Red 8 DAC Green 8 Blue 8

  16. VGA Controller component vga_controller_640_60 is port ( rst : in std_logic; clk50 : in std_logic; HS : out std_logic; VS : out std_logic; hcount : out std_logic_vector(10 downto 0); vcount : out std_logic_vector(10 downto 0); blank : out std_logic); end component; • Used in 525.442 (digilent) • Generates timing for 640x480 @ 60Hz • Free runs, you supply the pixel values directly to the DAC based on the values this component provides on hcount and vcount

  17. Image Memory Requirements • 640x480x3 = 921k bytes of memory to represent an entire VGA bitmap • Entire FPGA contains 1.5 Mbits of Block RAM • Use of DDR on board is one solution to this • More on this later • Reduce color space • less bits per color, • Greyscale • …etc. • Reduce real resolution • Numerous creative ways for computation of pixel values on the fly without direct storage of each pixel location • for the FFT display, there need only be 640 values stored (a magnitude scaled to be between 0 and 479 for each horizontal point) • For a waterfall display, one might only store the previous 100 or so magnitudes (8 bit) for each of the 640 values. (64k bytes)

  18. DDR Memory Interface

  19. Synchronous SRAM (NOT DDR) Read Cycle Accessing Synchronous SRAM fairly straightforward, easy to design, fairly relaxed timing. From IBM App Note Understanding Static RAM Operation, sramop.pdf

  20. Double Data Rate (DDR) Memory • Maximize throughput: • High clock rate (133+ MHz) • DDR, 100 – 200 MHz; DDR2, 200 – 533 MHz; DDR3: 400 – 800 MHz • Transfer data on both edges • Burst reads and writes • Short access times • Simple performance definition: • Frequency rate • 133 MHz, 166 MHz, etc. • CAS (Column Address Strobe) Latency (CL), in clock cycles • delay time between when a column access is requested, and the data is available

  21. From Micron MT46V16M16 datasheet

  22. From Micron MT46V16M16 datasheet

  23. DDR Timing Difficulties • Source synchronous: data and clock from data source • Clock at 166 MHz: • Period: 6 ns • Half Period: 3 ns • Routing from IOB to destination delays can easily vary from < .5 ns to > 2+ ns – a significant portion of our half-period! • IOB placement? • Destination placement? • More than 15 pages defining Input Timing alone in Spartan 3A Data Sheet

  24. Double Data Rate to Single Data Rate Clock delays determined during calibration at startup From DDR2 SDRAM Interface for Spartan-3 Generation FPGAs, xapp454.pdf

  25. MPMC: Multi-Port Memory ControllerMIG: Memory Interface Generator • Memory controller provided by Xilinx • Memory-side: • Provides interface to SDRAM, DDR, DDR2, DDR3, LPDDR memories • Fabric-side: • 8 Interfaces made available to FPGA fabric • MPMC handles the prioritization between parallel accesses to the external memory • Variety of interfaces: • PLB interface • Xilinx Cache Link (XCL) • PowerPC interface • Video Frame Buffer Controller (VFBC) • Native Port Interface

  26. PHY from MIG From Xilinx MPMC datasheet

  27. From Xilinx MPMC datasheet

  28. Personality Interface Modules (PIMs) • Xilinx CacheLink PIM (XCL): Provides a near direct connection to the MicroBlaze processor cache. • Soft Direct Memory Access Controller PIM for LocalLink Interfaces (SDMA): A 32-bit wide Xilinx Local Link interface provides medium-throughput performance, but offloads CPU involvement with hardware scatter-gather handling. Typically SDMA is used only with an XPS_LL_TEMAC core. • Processor Local Bus Version 4.6 PIM (PLB): A general interface used on most EDK IP cores. The PLB is suggested to be used for the most forward-compatibility. • PowerPC 440 Memory Controller PIM (PPC440MC): Provides lowest latency connection when using the Virtex-5 PowerPC 440 processor.. • Video Frame Buffer Controller PIM (VFBC): A two-dimensional DMA core which also provides asynchronous clocking from MPMC_Clk0. High-latency, but high-throughput operation for very long bursts, such as entire video frames. • Native Port Interface PIM (NPI): The highest performance general PIM. All other PIMs except for MCB connect through an NPI interface. • MCB PIM (MCB): Spartan-6 only PIM providing raw access to the hardened memory controller for highest performance.

  29. Example MPMC Use Case DDR Memory MPMC PHY MPMC XCL XCL VFBC VFBC VFBC VFBC Microblaze Convolution Core Camera VGA

  30. MPMC Configuration These ports are exposed to external FPGA fabric.

  31. MPMC Port Configuration

  32. Physical Interface Layer • Physical Interface Layer “performs the calibration and signaling to the external memory device”. • PHY options available: • Xilinx MIG: • Recommended interface for all FPGAs but Spartan 6 • Generated interface placed in specific FPGA resources to meet timing • Pin settings must be chosen during PCB design • Spartan 6: • Hard-core memory interface • Static PHY: • “Last-choice” memory interface • Includes clock-adjustment control so user can self-calibrate the clock-phasing

  33. MIG • Xilinx provides the “Memory Interface Generator” • Software tool that takes as inputs…: • Memory definition (speed, CAS, data width, banks, etc.) • FPGA part • Preferred input locations (sides, etc.) • …and produces: • RTL PHY • Pin locations • UCF file to define pins and place RTL PHY in specific LUTs, etc., with full set of constraints • PHY auto-calibrates: • Calibrates delay lines to keep delayed DQS correctly aligned across temperature/voltage variations

  34. PHY: Memory Interface Generator

  35. MIG: Setting Pin Locations

  36. Designing With MPMC • Design memory interface before laying out board • Select FPGA and memory • Using MIG before laying out board, determine required location for all memory interface signals

  37. Hard – Core Memory Controllers Spartan 6 and many new FPGAs have a hard memory control block on-die. Goal : eliminate all ucf wrangling and extended place/route time while increasing performance. Timing critical pieces simply exist in a proven piece of hardware.

  38. RST_DQS_DIV The FIFO write enable signal is generated from a signal named rst_dqs_div. Figure4 illustrates the idea behind rst_dqs_div. The rst_dqs_div signal is driven to an IOB as an output and is then taken as an input through the input buffer. This technique normalizes the IOB and trace delays between rst_dqs_div and the DQS clock signals. The rst_dqs_div from the input pad of the FPGA uses identical routing resources as the DQS before it enters the LUT delay circuit. The trace delay of the loop should be the sum of the trace delays of the clock forwarded to the memory and the DQS. Source: xapp454, DDR2 SDRAM Interface for Spartan-3 Generation FPGAs

  39. Oops

  40. UCF/Timing Report ############################################################################################################## ## Constraint from rst_dqs_div_in PAD to input of LUT delay element. ############################################################################################################## NET "*/DDR_SDRAM_MT46V16M16_5B/mpmc_core_0/gen_??_ddr_phy.mpmc_phy_if_0/dqs_div_rst" MAXDELAY = 468 ps; ================================================================================ Timing constraint: NET "Inst_processor/DDR_SDRAM_MT46V16M16_5B/DDR_SDRAM_MT46V16M16_5B/mpmc_core_0/ gen_s3_ddr_phy.mpmc_phy_if_0/dqs_div_rst" MAXDELAY = 0.468 ns; 1 net analyzed, 1 failing net detected. 1 timing error detected. Maximum net delay is 2.549ns. -------------------------------------------------------------------------------- Slack: -2.081ns Inst_processor/DDR_SDRAM_MT46V16M16_5B/DDR_SDRAM_MT46V16M16_5B/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/dqs_div_rst Error: 2.549ns delay exceeds 0.468ns timing constraint by 2.081ns From To Delay(ns) AB5.I SLICE_X0Y70.G3 2.499 AB5.I SLICE_X1Y70.F3 2.448 AB5.I SLICE_X1Y70.G4 2.481 AB5.I SLICE_X1Y71.G2 2.549 --------------------------------------------------------------------------------

  41. Adding Memory (Roughly) • Add a MPMC • During this process, add a memory that matches your part as closely as possible; update to match exactly • This adds a memory to the MB, as well as the memory controller PHY, but without constraints • Create a new Memory PHY in the ISE project • During this process, add a memory that matches your part as closely as possible; update to match exactly • Choose the banks where you would like the memory to go • Generate • Go back and edit to match your pins exactly; check with memory generator • Take the UCF from the Memory PHY, and map to the MPMC PHY • xilperl C:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\mpmc_v4_03_a\data\convert_ucf.pl --mhs …\processor.mhs …\mem_phy\user_design\par\mem_phy.ucf …\new.ucf • Incorporate into your UCF

  42. Sample Design • Instructors have the source and bitfile for a sample design which simply hooks the Microblaze to DDR memory • Provides Microblaze with large program/data space • Sample program performs memory test • Will be posted to website to download / run

  43. Backup

  44. DDR2 SDRAM Interface Module Source: xapp454, DDR2 SDRAM Interface for Spartan-3 Generation FPGAs

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