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Chapter 5

Chapter 5. The Inverter. April 10, 2003. Objective of This Chapter. Use Inverter to know basic CMOS Circuits Operations Watch for performance Index such as Speed (Delay) Optimal Transistor Sizing Power Consumption. V. DD. V. V. in. out. C. L. The CMOS Inverter: A First Glance. V.

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Chapter 5

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  1. Chapter 5 The Inverter April 10, 2003

  2. Objective of This Chapter • Use Inverter to know basic CMOS Circuits Operations • Watch for performance Index such as • Speed (Delay) • Optimal Transistor Sizing • Power Consumption

  3. V DD V V in out C L The CMOS Inverter: A First Glance

  4. V DD CMOS Inverter N Well PMOS 2l Contacts Out In Metal 1 Polysilicon NMOS GND

  5. Two Inverters Share power and ground Abut cells Connect in Metal Vin Vout Vout Vin

  6. V V DD DD R p V out V out R n V V V 0 = = in DD in CMOS InverterFirst-Order DC Analysis VOL = 0 VOH = VDD VM = f(Rn, Rp) Rn, Rp: Channel Resistance in Saturation Mode

  7. t = f(R .C ) pHL on L = 0.69 R C on L CMOS Inverter: Transient Response V V DD DD R p V out V out C L C L R n V 0 V V = = in DD in (a) Low-to-high (b) High-to-low

  8. Voltage TransferCharacteristic

  9. I Dn V = V +V in DD GS,p I = - I D,n D,p V = V +V out DD DS,p V out I I I Dp Dn Dn V =0 V =0 in in V =1.5 V =1.5 in in V V V DS,p DS,p out V =-1 GSp V =-2.5 GSp V = V +V V = V +V in DD GSp out DD DSp I = - I Dn Dp PMOS Load Lines (Vdd = 2.5V)

  10. CMOS Inverter Load Characteristics

  11. CMOS Inverter VTC VM: Vin = Vout

  12. Switching Threshold as a Function of Transistor Ratio NMOS and PMOS are in Saturation Modes For r = 1, and mobility NMOS = 2 PMOS, Wp = 2Wn

  13. (V) V Switching Threshold as a Function of Transistor Ratio 1.8 1.7 1.6 1.5 1.4 1.3 M 1.2 1.1 1 0.9 0.8 0 1 10 10 /W W p n

  14. Simulated VTC

  15. 2.5 2 Good PMOS Bad NMOS 1.5 Nominal (V) out Good NMOS Bad PMOS V 1 0.5 0 0 0.5 1 1.5 2 2.5 V (V) in Impact of Process Variations

  16. Propagation Delay

  17. CMOS Inverter Propagation DelayApproach 1

  18. CMOS Inverter Propagation DelayApproach 2

  19. V DD PMOS Metal1 Polysilicon NMOS CMOS Inverters 1.2 m m =2l Out In GND

  20. Transient Response ? tp = 0.69 CL (Reqn+Reqp)/2 tpHL tpLH

  21. Design for Performance • Keep loading capacitances (CL) small • Increase transistor sizes (add CMOS gain) • Watch out for self-loading (for the previous stage)! • Increase VDD (????)

  22. Delay as a function of VDD

  23. Device Sizing (for fixed load) Self-loading effect: Intrinsic capacitances dominate

  24. NMOS/PMOS ratio tpHL tpLH tp b = Wp/Wn

  25. Impact of Rise Time on Delay

  26. Inverter Sizing

  27. Inverter Chain In Out CL • If CL is given: • How many stages are needed to minimize the delay? • How to size the inverters? • May need some additional constraints.

  28. Inverter Delay • Minimum length devices, L=0.25mm • Assume that for WP = 2WN =2W • same pull-up and pull-down currents • approx. equal resistances RN = RP • approx. equal rise tpLH and fall tpHL delays • Analyze as an RC network 2W W tpHL = (ln 2) RNCL Delay (D): tpLH = (ln 2) RPCL Load for the next stage:

  29. Inverter with Load Delay RW CL RW Load (CL) tp = kRWCL k is a constant, equal to 0.69 Assumptions: no load -> zero delay Wunit = 1

  30. Inverter with Load CP = 2Cunit Delay 2W Cint CL W Load CN = Cunit Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint) = Delay (Internal) + Delay (Load)

  31. Delay Formula Cint = gCgin withg 1 f = CL/Cgin- effective fanout R = Runit/W ; Cint =WCunit tp0 = 0.69RunitCunit

  32. Apply to Inverter Chain In Out CL 1 2 N tp = tp1 + tp2 + …+ tpN

  33. Optimal Tapering for Given N • Delay equation has (N-1) unknowns, Cgin,2 – Cgin,N • Minimize the delay, find N - 1 partial derivatives • Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1 • Size of each stage is the geometric mean of two neighbors • Each stage has the same effective fanout (Cout/Cin) • Each stage has the same delay

  34. Optimum Delay and Number of Stages When each stage is sized by f and has same effective fanout f: Effective fanout of each stage: Minimum path delay

  35. Example In Out CL= 8 C1 1 f f2 C1 CL/C1 has to be evenly distributed across N = 3 stages:

  36. Optimum Number of Stages For a given load, CL and given input capacitance Cin Find optimal sizing f For g = 0, f = e, N = lnF

  37. Optimum Effective Fanout f Optimum f for given process defined by g fopt = 3.6 forg=1

  38. Impact of Self-Loading on tp No Self-Loading, g=0 With Self-Loading g=1

  39. Normalized delay function of F

  40. Buffer Design N f tp 1 64 65 2 8 18 3 4 15 4 2.8 15.3 1 64 1 8 64 1 4 64 16 1 64 22.6 8 2.8

  41. Power Dissipation

  42. Where Does Power Go in CMOS?

  43. Vdd Vin Vout C L Dynamic Power Dissipation 2 Energy/transition = C * V L dd 2 Power = Energy/transition * f = C * V * f L dd Not a function of transistor sizes! Need to reduce C , V , and f to reduce power. L dd

  44. Modification for Circuits with Reduced Swing

  45. Node Transition Activity and Power

  46. Transistor Sizing for Minimum Energy • Goal: Minimize Energy of whole circuit • Design parameters: f and VDD • tp tpref of circuit with f=1 and VDD =Vref

  47. Transistor Sizing (2) • Performance Constraint (g=1) • Energy for single Transition

  48. Transistor Sizing (3) VDD=f(f) E/Eref=f(f) F=1 2 5 10 20

  49. Short Circuit Currents

  50. How to keep Short-Circuit Currents Low? Short circuit current goes to zero if tfall >> trise, but can’t do this for cascade logic, so ...

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