The Design of Hybrid Carry-Lookahead/Carry Select Adders

1. The Design of Hybrid Carry-Lookahead/Carry Select Adders Yuke Wang , C. Pai Xiaoyu Song Member IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II:ANALOG AND DIGITAL SIGNAL PROCESSING,VOL.49,NO.1,JAN.2002

2. Outline • Introduction • General Architecture Of The Hybrid CLA/CSA • New Implementation Of Hybrid CLA/CSA • Performance Evaluation • Conclusion

3. Introduction • Importance of addition • Different adders use different implementation • STCLA(spanning tree CLA) • RCLCSA(recursive CLA/CSA) • HSAC(high-speed CLA) • Hybrid CLA/CSA Dynamic CMOS Static CMOS Both Above

4. Outline • Introduction • General Architecture Of The Hybrid CLA/CSA • General Architecture • Dynamical Logic Implementation • Static Logic Implementation • New Implementation Of Hybrid CLA/CSA • Performance Evaluation • Conclusion

5. A General Architecture Of The Hybrid CLA/CSA • Structure Carry Lookahead Unit -bit Carry Select Adder a b -bit Carry Select Adder Cin -bit Carry Select Adder

6. A General Architecture Of The Hybrid CLA/CSA(1/2) • Propagate signal : • Generator signal : • Sum : • Carry :

7. A General Architecture Of The Hybrid CLA/CSA(2/2) • Different technolgy implementation • Hybrid CLAs and CSAs not generate all propagate and generate signals

8. Dynamical Logic Implementation • 56-bit STCLA generates , , , , using a tree of MMC modules • 56-bit RCLCSA uses MMC with various lengths instead of fixed 4-bit chain , it generates , ,

9. Static Logic Implementation(1/2) Cin a/b[ : ] a/b[ : ] a/b[ : ] a/b[ : ] a/b[ : ] a/b[ : ] a/b[ : ] a/b[ : ] a/b[ : ] a/b[ : ] a/b[ : ] a/b[ : ] a/b[ : ] a/b[ : ] a/b[ : ] a/b[ : ] 52 49 37 19 10 7 4 55 46 43 40 25 22 16 13 1 50 47 35 17 8 5 2 53 44 31 38 23 20 14 11 0 G0 G2 G1 G0 G2 G1 G0 G2 G1 G0 G2 G1 G0 G2 G1 G0 Block 6 Block 5 Block 4 Block 2 Block 1 Block 0 Gloval Carry Lookahead

10. Static Logic Implementation(2/2) • For simplicity , we define , , … , , …

11. New Implementation Of Hybrid CLA/CSA(1/4)

12. New Implementation Of Hybrid CLA/CSA(2/4) • Complement Ling’s carries

13. New Implementation Of Hybrid CLA/CSA(3/4) • H expression :

14. New Implementation Of Hybrid CLA/CSA(4/4) Inverted MUX Global Lookahead Unit Carry Select Adder

15. Outline • Introduction • General Architecture Of The Hybrid CLA/CSA • New Implementation Of Hybrid CLA/CSA • Performance Evaluation • Performance Evaluation Model • Critical Paths of the Adders • Conclusion

16. Performance Evaluation Model • Different implementation methods is not accurate at all

17. Critical Paths Of The Adders(1/2) • Definition of critical path • Critical path in adders • Transistor delay models

18. Critical Paths Of The Adders(2/2)

19. Conclusion • This is a general architecture for hybrid CLA/CSA adders • The new implementation ca be in static CMOS or dynamic logic style • The critical path of the new implementation is about 2/3 of the old adders • In reality , the difference of speed between new adders and others is less than 1/3

20. Improvement(1/2) • The new adders doesn’t implement at this paper , I should have to verify the theorem • In CLA and CSA blocks , we can use multilevel to improve its speed • I will try different lengths of each block instead of fixed lengths

21. Improvement(2/2)