1 / 49

Status of the electronic systems of the MEG Experiment

This article provides an overview of the current status of the electronic systems used in the MEG experiment, including the trigger system and the active splitter. It also discusses the redesign of the splitter and the testing of new components.

gadames
Download Presentation

Status of the electronic systems of the MEG Experiment

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Status of the electronic systems of the MEG Experiment Pietro Creti Stefano Giurgola Marco Grassi Fabio Morsani Donato Nicolo Wataru Ootani Marco Panareo Stefan Ritt Matthias Schneebeli Giovanni Signorelli

  2. Topics 800 + 160 area ~3m Trigger ~11m Active Splitter 3+1 VME crates PMT monitor trigger ready 5 VME crates ~3m optical fiber (~20m) DRS Board (32chn) + CPU Front-End PCs Rack – PC (Linux) SIS 3100 Rack – PC (Linux) Rack – PC (Linux) 1920 ~7m Rack – PC (Linux) DRS Board (32chn) + CPU DC Pre-Amp Rack – PC (Linux) Rack – PC (Linux) Rack – PC (Linux) Rack – PC (Linux) Rack – PC (Linux) Rack – PC (Linux) Rack – PC (Linux) On-line farm

  3. Active Splitters Status

  4. input DRS output Monitor output test Trigger output Sum output Original splitter structure • High gain, low noise first stage to reduce total noise. • Low distortion second stage to drive the outputs. • 4 input adder. • Precise layout design to reduce parasitic coupling. • Defined impedance striplines for the interconnections.

  5. Prototypes • In July 2004 a 8-channels 6U prototypes was ready • The prototype was tested in Lecce with the help of Y. Yudin. • Then we realized a 4-layer printed circuit, and we built 2 card with a mini-crate and power supply.

  6. Splitter redesign • At the PSI July meeting we decide to modify the output lines from single-ended to differential, to reduce the crosstalk at the DRS input. • This choice required a complete redesign of the card. • Moreover we evaluated the possibility to use flat (twisted) cable to connect the splitter outputs to the DRS inputs. input Spare test DRS output Trigger output Sum output Differential

  7. New components • AD8009 - 1GHz, 5500 V/μs Low Distortion Amplifier • Amplifier stages and adder; • AD8351 Low Distortion Differential RF/IF Amplifier • DRS and sum outputs driver; • AD8137 – Low Distortion Differential ADC Driver • Differential output driver. 2004 manufactured

  8. New prototype • Test of new chips and interconnections: new 4-channels prototype • Currently under test

  9. Preliminary measurements Input : 46.0mV, tf: 2.4 ns Out 1 : 311mV, tr: 2.5 ns Out 2 : 307mV, tf: 1.5 ns Diff : 619mV, tf: 1.6 ns

  10. Preliminary measurements f =100MHz Integral non-linearity: <2% (0mV÷50mV)

  11. Preliminary measurements • Crosstalk level is about 14mVpp, having a signal of ±1.7V on the adjacent channel • So we conclude that crosstalk is below 1% • noise level at about 1mVpp Crosstalk Noise

  12. Temperature dependence Propagation delay coefficient < 2ps/°C

  13. Distortion measurement Difference between Vin∙Av and Vout Vin rise time

  14. Towards the final system • Test of this prototype with the DRS and the trigger board • Study of the maximum channel density compatible with the routing on a standard format (6U, 9U, …) card. June 2005 • Design of the final board September 2005

  15. Cable tests • Input signal: rectangular pulse of 14 ns with 0.9ns rise time and 0.9ns fall time • Quality parameter: rise time of the output pulse • For short lengths (~2m) the flat twisted cable (green curve) is equivalent to the coaxial ones. • Splitter outputs: differential on twisted pairs • The 3M coaxial solution uses the RG178B/U (black curve) which have the worst performances • Splitter inputs: optimization of connectors, cable type and length is necessary

  16. Trigger System status

  17. Reminder trigger observables • energy, direction and time (LXe calorimeter) • e+time and approx. direction (Timing Counters) Digital approach • Flash analog-to-digital converters (FADC) • Field programmable gate array (FPGA) Expected rate • For 108 muon stop rate

  18. Trigger types MEG trigger • makes use of allvariables of the photons and the positrons with baseline algorithms Efficiency-debugging triggers • like MEG trigger but relaxing 1 selection criteria Calibration triggers • selection of e events for timing calibration • selection of induced physical events (LED, α, π0, laser); • the connection of auxiliary external devices (like calorimeters, laser) occurs through further Type1 boards Alternative triggers • trigger hardware is dimensioned to support other algorithms (Principal Component Analysis)

  19. MEG Trigger QSUM > QTH&&(z,) DWN&&|T| < TWN QTL QTH DWW DWN MeV Efficiency-debugging triggers Charge:QSUM > QTL&&(z,) DWN&&|T| < TWN Direction:QSUM > QTH&&(z,) DWW&&|T| < TWN Time:QSUM > QTH&& (z,) DWN&&|T| < TWW

  20. Calibration Triggers Alpha :PMT patches on lateral faces near the source wires QPATCH>QTPATCH &&QSUM< QTL&&|T| >TWW p0 :Use of auxiliary external devices (calorim. and ptiming counter) QSUM>QTL&&QAUX >QTAUX&&|TAUX|<TWN LXe single :high thr.QSUM> QTH, low thr.QSUM > QTL e : narrow coinc.QSUM> QTL&&|T| > TWN wide coinc.QSUM> QTL&&|T| > TWW Baseline:internally generated random triggers for DRS baseline evaluation LED:use of LED driver signal LASER: reference Laser PMT signal > Laser Thr DC trigger: use of a wire layer of the drift chambers

  21. Various features All triggers can be: • masked • prescaled(up to 65535 counts) Other stored information Type 1 • Single rate for each PMT Type 2 • Rate for each trigger type • Event Counter (hardware distributed to the DRS boards) • Trigger pattern (hardware distributed to the DRS boards) • Live Time and Dead Time

  22. 14 boards . . . Type2 Type2 Type2 Type2 Type2 Type2 15x 48 11 boards Type1 Type1 Type1 Type1 Type1 Type1 Type1 Type1 Type1 Type1 Type1 11x 48 4 4 4 4 16 16 16 16 9 boards 2 x 48 4 x 48 2 x 48 . . . 9x 48 Trigger system structure 2 boards LXe inner face (216 PMTs) . . . LXe lateral faces back (216 PMTs) 4 in 1 lat. (144x2 PMTs) 4 in 1 up/down (54x2 PMTs) 4 in 1 2 boards 1 board 4 x 48 Timing counters curved (640 APDs) 8 in 1 u/d stream (30x2 PMTs) 1 board 2 VME 6U 1 VME 9U Located on the platform 2 boards . . . Drift chambers 2 x 16 groups of wire fan in 2 x 48

  23. Number of boards: summary table

  24. Information flow LXe inner face SUMPMT: Sum of PMT charge MAXPMT: Charge of the PMT that has seen maximum light yield INDMAX: index of the PMT that has seen maximum charge S: Saturation bit. Warns whether PMT saturation occurs TIMPMT: index of the PMT that has seen maximum charge

  25. Information flow other LXe faces SUMPMT: Sum of PMT charge PARTIAL SUM: Sum of the PMT charge for PMT belonging to the same patch IND SUM: Index of the Patch that has seen a charge over a min. threshold

  26. Information flow TC and AUX devices TTIM: Time registered TC bar INDTIM: Index of TC bar ZTIM: Position on the TC bar along the z direction

  27. Type1 Present Status CPLD : Coolrunner II (XC2C284-10-FG324)  • Type1 : CPLD design completed and simulated FPGA : VIRTEX II- PRO (XC2VP20-7-FF1152) • Type1-1: FPGA design with ISE 6.3 completed (Frequency 116 MHz) • Type1-1: FPGA simulation completed  • Type1-2 (LXe lateral faces) in progress~ • Type1-3 (TCs)x PCB : • import FPGA • Board Schematics • Footprints • Routingin progress~ • Gerber filesx

  28. Type2 Present Status CPLD : Coolrunner II (XC2C284-10-FG324)  • Type1 : CPLD design completed and simulated FPGA : VIRTEX II- PRO (XC2VP40-7-FF1152) • Type2-0 (Final Level): FPGA design with ISE 6.3 completed   • Type2-0: FPGA simulation in progress~ • Type2-1 (LXe inner faces) x • Type2-2 (LXe lateral faces) x • Type2-3 (TCs)x PCB : • import FPGA • Board Schematicsin progress~ • Footprints  • Routingx • Gerber filesx

  29. Ancillaryboards Type2 Type2 Type2 Type1 Type1 Type1 Type1 Type1 Type1 5 5 2 5 5 2 5 5 Event counter Trigger pattern to DRS Busy from DAQ START STOP START STOP SYNC RES CLK ANCILLARY Mother . . . CLK 20 MHz SYNC RES VME ANCILLARY Daughters CLK to DRS

  30. Trigger schedule 2002 2003 2004 2005 Prototype Board Final Prototype Full System partial installation Prototype Board Final Prototype Full system 1st lot of components ordered full install. 2nd lot of components Design Manufactoring Assembly Test Milestone

  31. DRS status

  32. Current mode readout • First implemented in DRS2 (DRS1 had charge readout) • Sampled charge does not leave chip • Current readout less sensitive to charge injection (noise) and cross-talk R (700 ) I Uin Uout read write . . . C (200fF)

  33. Frequency stabilization • Compensate for temperature drifts • Change Vspeed only between events, keep stable during acquisition phase • Jitter ~ 150ps • Timing accuracy with 9th channel <25ps 150ps Vspeed FPGA Frequency Counter 16-bit DAC LUT

  34. Measured DRS2 Parameters • Linear response up to 400mV • Usable range of 1V p-p • Speed range 0.5 GHz – 4.2 GHz DRS2 response UOUT (mV) f (GHz) UIN (mV)

  35. DAQ Boards PSI GVME Board FPGA with 2 Power-PC

  36. LP waveforms 2 DRS digitizing LP signals • 8ch for data and 2ch for calib. • 2.5GHz sampling • 1024 sampling cells • Readout at 40MHz 16bit • trigger from LP DRS inputs • LP: central 12 PMTs • LYSO: two signals for each DRS

  37. Big spikes • Big spikes are in phase with the time reference clock • The cross-talk is on the mezzanine board • It will disappear with a new redesign board • The internal cross-talk is already much lower Xe Time reference

  38. correct phase Charge injection from stage switch wrong phase Small spikes The readout phase is controlled by the FPGA: it can be adjusted

  39. Baseline dependence on cell # UOUT (mV) UOUT (mV) Cell # Cell # Intrinsic and expected characteristic R=700 W U R=~20 W 16 x 64 cells

  40. DRS calibration Needs of individual response function for each cell UOUT (mV) UIN (mV)

  41. DRS Calibration • Calibrations of the two DRS chips used in the CEX test were completed by MS and implemented in the “lpframework”. • Very helpful especially for analyzing small signal (alpha event) • There’s still spike structure left, which is expected to disappear in the next version of the DRS. Xe(γ) Xe(α)

  42. Signal-to-noise ratio • 1 V DC input signal, common mode subtracted • Individual bin has RMS of 2 mV → SNR = 500:1 (9 bit) • Integration over 100 ns PMT pulse (250 bins) has RMS of0.16 mV → SNR = 6200:1 (12.6 bit) • Could be improved by better analog design of Mezzanine board mV mV

  43. Waveforms Xe(γ) Xe(α) LYSO

  44. Time constant γ a Pulse height [mV] Analysis examples • Alpha events are clearly discriminated from gamma event. • LYSO time resolution is approaching intrinsic resolution determined by TDC Pulse shape discrimination LYSO time resolution

  45. Averaged Waveform • Averaged waveform can be used for waveform fitting as a template, for simulating pileup and for testing analysis algorithm, etc. • The measured waveforms are averaged after synchronizing them with T0 calculated by waveform fitting so as not to smear leading edge. Average Xe Xe Average LYSO LYSO

  46. Fitting with Averaged Waveform • Averaged waveform is nicely fitted to waveform of any height. • Pulse shape seems to be fairly constant from event to event for gamma event.

  47. Pileup Rejection • Overlapping pulses are simulated using averaged waveform to test rejection algorithm. • Real baseline data obtained by the DRSs is used. Npe1=2000phe Npe2=1000phe (3000phe is typical for 50MeV gamma) ΔT=+30nsec ΔT=+60nsec ΔT=-30nsec

  48. Plans • Correct wrong sampling phase  • New analog design of mezzanine board in progress~ • New order of DRS2 issued on Jan 22nd 2005 • Chips will arrive ~May 2005 • 2000 channels in total • Enough for LXe calorimeter • Will be replaced with DRS3 • Redesign of DRS2 in spring 2005. DRS3 will be available at the end of 2005 • Better SNR (12 bit vs. 9 bit ?) • Smaller readout dead time

  49. Schedule 2002 2003 2004 2005 DRS1 Tests DRS2 2nd Prototype Boards & Chip Test DRS1 DRS2 DRS2 production 1600 chn DRS2 test board DRS3 Mass Production 3000 chn 1600 chn 400 chn VME boards Full System Milestone Design Manufactoring Assembly Test installation

More Related