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ME 4447/6405

Microprocessor Control of Manufacturing Systems and Introduction to Mechatronics Instructor: Professor Charles Ume Timers. ME 4447/6405. The Timer Sub-system Includes these Distinct Features: 16-bit Counter Seven-Stage Programmable Prescaling Eight Input Capture Channels

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ME 4447/6405

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  1. Microprocessor Control of Manufacturing Systems and Introduction to Mechatronics Instructor: Professor Charles Ume Timers ME 4447/6405

  2. The Timer Sub-system Includes these Distinct Features: 16-bit Counter Seven-Stage Programmable Prescaling Eight Input Capture Channels Eight Output Compare Channels 16-bit Pulse Accumulator Lecture Outline

  3. Look at Page 31 in Reference Manual for Actual Register Addresses Central element of timer:16-bit free running counter At reset counter is disabled Once enabled, counter starts from $0000 and counts up continuously When $FFFF is reached, counter rolls over to $0000 Cannot be written to during operation (only writable in test mode) May be reset upon successful Output Compare 7 General Description of Main Timer Bit 15 - - - - - - Bit 8 $0044 TCNT $0045 Bit 7 - - - - - - Bit 0

  4. Timer Enable (TEN) bit determines operation of the timer and counter Writing a 1 to TEN turns on the counter, writing a 0 disables the system, reducing power consumption 7 6 5 4 3 2 1 0 TSCR1 TEN TSWAI TSFRZ TFFCA 0 0 0 0 $0046 Enabling the Free-Running Counter

  5. Allows 8 clocking rates of the timer counter E-Clock rate divided by: 1, 2, 4, 8, 16, 32, 64, 128 At reset the default prescale factor is 1 Prescale may be changed at any time Will take effect after some number of clock cycles where all prescale counter stages equal zero. (see p. 450 of Family Reference Manual for details) Counter Prescaler

  6. Note: Clock frequency is 8 MHz Trade-off between timer resolution and timer range 7 6 5 4 3 2 1 0 $004D TSCR2 TOI 0 0 0 TCRE PR2 PR1 PR0 Changing the Counter Prescaler

  7. Timer overflow flag (TOF) status bit set each time the counter rolls over from $FFFF to $0000 TOF status bit can generate an automatic interrupt request by setting the timer overflow interrupt (TOI) enable bit 7 6 5 4 3 2 1 0 TFLG2 TOF 0 0 0 0 0 0 0 $004F 7 6 5 4 3 2 1 0 TSCR2 TOI 0 0 0 TCRE PR2 PR1 PR0 $004D Counter Overflows

  8. Interrupt Vector Table • MON12 in use • Standard S12C32 Interrupt Vector Jump Table is not available with MON12 • MON12 supplies alternate Interrupt Jump Table • User’s interrupt service routine must be stored in $4000-$7FFF (External RAM) if Autostart is to be used Monitor Interrupt Vector Table (CML-C32 User’s Guide)

  9. Extending the range of the 16-bit counter with an 8-bit software counter Software keeps track of counter overflows Creates a 24-bit counter (16-bit + 8-bit) Time values are stored as 3-byte numbers Measuring Long Periods Using Counter Overflow

  10. Each of the eight I/O pins of Port T may be used as either an input capture or an output compare If IOSX is 0, the corresponding channel acts as an input capture If IOSX is 1, the corresponding channel acts as an output compare Input Capture Vs. Output Compare

  11. Used to record time event occurs When input signal is received by input capture channel Contents of free-running counter is transferred to 16-bit register corresponding to that input capture channel Input Capture Concept

  12. 16-bit registers Input edge-detection logic Interrupt generation logic Features of Input Capture Function

  13. Eight 16-bit input capture registers are available Each register has a corresponding timer input pin (TC0-TC7) located on Port T pins PT0-PT7 When edge is detected at timer input pin, current value of free-running counter is stored in corresponding input capture register Input Capture Registers

  14. Can be read at any time as a pair of 8-bit registers using instructions like LDD or LDX Writing to register when used as Input Capture has no meaning Input Capture Registers (cont’d) Bit 15 - - - - - - Bit 8 $0050 TC0 $0051 Bit 7 - - - - - - Bit 0 … Bit 15 - - - - - - Bit 8 $005E TC7 $005F Bit 7 - - - - - - Bit 0

  15. Used to select which edge of input signal is detected 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 TCTL4 TCTL3 EDG3B EDG7B EDG3A EDG7A EDG2B EDG6B EDG6A EDG2A EDG5B EDG1B EDG1A EDG5A EDG0B EDG4B EDG0A EDG4A $004B $004A Input Edge-Detection Logic

  16. Input capture status flags are automatically set to one each time a selected edge is detected Input capture interrupt enable bits If CXI is 1when CXF is set, interrupt condition is met 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 TIE TFLG1 C7F C7I C6I C6F C5I C5F C4F C4I C3F C3I C2I C2F C1I C1F C0I C0F $004E $004C Interrupt Generation Logic

  17. Period or frequency measurement Capture the time of two successive rising or falling edges Pulse width measurement Capture the time between two adjacent edges Application of Input Captures

  18. FIRST EQU $2000 DEFINE A 2-BYTE LOCATION TO STORE FIRST EDGE PERIOD EQU $2002 DEFINE A 2-BYTE LOCATION TO STORE PERIOD ORG $1000 LDAA #$80 STAA $0046 ENABLES FREE RUNNING COUNTER LDAA #$00 ENSURES PT1 IS USED AS AN INPUT CAPTURE STAA $0040 NOTE: THIS IS THE CASE BY DEFAULT LDAA #$04 ie Input Capture 1 is being used STAA $004B EDGE DETECTION FOR IC1 SET TO RISING EDGES LDAA #$02 STAA $004E CLEARS ANY OLD FLAGS FROM IC1F LOOP1 BRCLR $4E #$02 LOOP1 LOOP HERE UNTIL FIRST RISING EDGE IS DETECTED LDD $0052 READ TIME OF FIRST CAPTURE STD FIRST STORE FIRST CAPTURE VALUE LDAA #$02 STAA $004E CLEAR THE IC1F FLAG BEFORE NEXT EDGE LOOP2 BRCLR $4E #$02 LOOP2 LOOP HERE UNTIL NEXT RISING EDGE IS DETECTED LDD $0052 READ TIME OF SECOND CAPTURE SUBD FIRST FIND THE TIME DIFFERENCE BEWTEEN EDGES STD PERIOD STORE THE RESULT AS THE PERIOD (cycles) : : : Period Measurement Example Code

  19. Can be used as time reference for output function. Input capture records event time Offset representing time delay is added to input capture and stored to output compare. Both input captures and output compares are referenced from same counter, so software latencies do not affect accuracy to time delay Application of Input Captures (cont’)

  20. Can be used as general purpose I/O pins when the timer functions are not needed Logic levels can be read even if input-capture function is enabled Can serve as flexible interrupt input pins Have some advantages over IRQ pin Other Uses of Input Capture Pins

  21. Output Compare: Basic Concept • • 8 Output Compare Registers to store numbers: • Each is 16-Bit Register • • 8 comparators-one for each channel • Comparator checks Number against Free Running Counter (TCNT Register) • This is done in hardware, no processor time used • •When Counter matches TCx Register, it triggers an event

  22. What “Event” is triggered? • Three Non-Exclusive Possibilities: • Changes output of: • One of port T pins if either of registers corresponding to Output Compare 0 to 6 successfully compares to TCNT register • One/several of Port T pins if Output Compare 7 register successfully compares to TCNT register • Set a Flag in TFLG Register • Cause an Interrupt

  23. Output Compare 0 PT0 Output Compare 1 PT1 Output Compare 2 PT2 Output Compare 3 PT3 Output Compare 4 PT4 Output Compare 5 PT5 Output Compare 6 PT6 Output Compare causes Port T Pins to change state (Part I) • Output Compares 0 to 6: • Each Output compare controls a SINGLE PIN:

  24. Output Compare causes Port T Pins to change state (Part II) • Output Compares 0 to 6: • TCTL1 ($0048) and TCTL2 ($0049) Registers Control How Each Pin Changes TCTL1 $1020

  25. Output Compare causes Port T Pins to change state (Part II)

  26. OC7M7 OC7D7 OC7M6 OC7D6 OC7M5 OC7D5 OC7M4 OC7D4 OC7D3 OC7M3 OC7M2 OC7D2 OC7D1 OC7M1 OC7D0 OC7M0 Output Compare causes Port T Pins to change state (Part III) • Output Compare 7: • Causes 8 Port T pins to change simultaneously • Notice PT0-PT6 are also used by Output Compares 0-6 • Successful channel 7 compare overrides any channel 0:6 compares Output Compare 7 Mask Register (OC7M) determines which Port T Pins will be Controlled by Successful Output Compare 7 PA0 PA2 PA1 PA7 PA6 PA5 PA4 PA3 OC7M $0042 OC7D Register sets value to be written to Port T pins selected in OC7M Rgister OC7D $0043

  27. 7 6 5 4 3 2 1 0 TFLG1 C7F C6F C5F C4F C3F C2F C1F C0F $004E Output Compare Causes Flag to Be Set (Part I) When Output Compare is successful it sets corresponding Flag in TFLG1 Control Register: Software must constantly poll TFG1 register to check for flags

  28. Output Compare Causes Flag to be Set part (II) You clear the Flag by writing a 1 to the corresponding Bit in TFLG ! You Must clear the Flag after it is set • Use LDAA, STAA commands to write 1 to Flag But DON’T USE BSET!!!!

  29. 7 6 5 4 3 2 1 0 TIE C7I C6I C5I C4I C3I C2I C1I C0I $004C Output Compare Causes a Interrupt Successful Output compare will cause an interrupt when corresponding bit in TIE is set:

  30. Measuring Long Intervals: Problems with Overflow Bit You must measure this length of time t Record Start Time Record End Time time t But I only have this much time to record last overflow …then I need to record the end time! This is where timer rolls over (overflow) t = [TEND-TSTART]+(# of overflows)*(Toverflow)

  31. CFORC $0041 FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0 Forced Output If you need to change state of Port T Pin BEFORE output compare occurs • Use Forced Output • Software triggers compare to occur • Pin T will change state accordingly. • For Forced Compare, Flag is not set. • Forced Compare takes precedence over regular compare if both occur at same time in same channel • No Flag will be set.

  32. Features: 16-bit Counter Incremented by: Edge on pin Logic level of pin Used to measure: Duration of pulse Number of events Pulse Accumulator Overview

  33. Can be read or written to at any time 2 Modes Event Counter Gated Time Accumulation Pulse Accumulator Input Pin: Port T Pin 7 Registers Key Things to Know

  34. PACNT $0062 & $0063 16 Bit PA Count PACTL $0060 PAFLG $0061 B15 B8 B7 B0 Pulse Accumulator Registers

  35. PAEN: 0 = Disabled, 1 = Enabled PAMOD: 0 = Event Counter, 1 = Gated Time PEDGE: Event Counter: 0 : Falling Edges, 1 : Rising Edges Gated Time: 0 : IOC7 input pin high enables bus clock divided by 64 clock to pulse Accumulator, and trailing falling edge on IOC7 sets PAIF flag 1: IOC7 input pin low enables bus clock divided by 64 clock to pulse Accumulator, and trailing rising edge on IOC7 sets PAIF flag Register Settings

  36. CLK[0:1]: Timer Clock Selection (See page 454 Reference Manual) PAOVF: 0 = No Overflow, 1 = Overflow PAOVI: 0 = Polling, 1 = Interrupt-Driven PAIF: 0 = No Trailing Falling Edge Detected, 1 = Trailing Rising Edge Detected PAIF: 0 = No Trailing Rising Edge Detected, 1 = Trailing Falling Edge Detected PAI: 0 = Polling, 1 = Interrupt-Driven Register Settings

  37. PAMOD = 0 Counts Active Edge of PAI pin Example: (PACNT = 0; PAEN = 1; PEDGE = 1) PAI PT7/ IOC7 16-BIT COUNTER PACNT Value 1 2 3 4 PACNT Event Counting Mode

  38. A light emitter/detector pair can be used in an assembly line to count the number of parts going by. Event Counting Example

  39. PAMOD = 1 Free-running bus clock divided by 64 Subject to PT7/IOC7 pin being active bus/64 CLOCK (from Main Timer) Clock PT7/ IOC7 AND 16-BIT COUNTER PACNT Gated Time Accumulation Mode

  40. PACNT = 0; PAEN = 1; PEDGE = 1 (inhibit counting when PT7/IOC7 is 1) bus/64 PT7 is set to 0 PACNT Value 1 2 3 4 5 6 Gated Time Example

  41. Common use of Gated mode Measure duration of single pulses Easier than with Input Capture Counter is zero before pulse starts After pulse, pulse time directly read (need starting and ending count for input capture) Pulse Width Measurement

  42. Gated Time Accumulation (PAMOD = 1) Set Pulse Accumulator to cause interrupt to occur after 5ms Steps: Calculate time for one bus/64 cycle Divide delay by time for one bus/64 cycle Take 2’s complement and store in PACNT When input goes to active level, counter will increment until overflow Example:Interrupt at Specified Time

  43. LDAA #$01 STAA PAFLG ; Clear PAIF by writing 1 to it LDAA #$41 ; PAEN = 1, PAMOD = 0, PEDGE = 0, PAI = 1 STAA PACTL Assembly Code: Initialization to Count Negative (falling) Edges

  44. Questions???

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