Topics

1. Topics • Logic synthesis. • Placement and routing.

2. Logic optimization • Logic synthesis programs transform Boolean expressions into logic gate networks in a particular library. • Optimization goals: minimize area, meet delay constraint; some power optimizations.

3. Syntax-directed translation • Translate HDL into logic directly. • ab + ac • Generally requires optimization.

4. Macros • Pre-designed logic. • Generally identified by language features. • + operator. • xxx() • Hard macro: includes placement. • Soft macro: no placement.

5. Logic synthesis phases • Technology-independent optimizations work on logic representations that do not directly model logic gates. • Technology-dependent optimizations work in the available set of logic gates. • Transformation from technology-independent to technology-dependent is called library binding.

6. Technology-independent optimizations • Works on Boolean expression equivalent. • Estimates size based on number of literals. • Uses factorization, resubstitution, minimization, etc. to optimize logic. • Technology-independent phase uses simple delay models.

7. Technology-dependent optimizations • Maps Boolean expressions into a particular cell library. • Mapping may take into account area, delay. • May perform some optimizations on addition to simple mapping. • Allows more accurate delay models.

8. Boolean network • A Boolean network is the main representation of the logic functions for technology independent optimizations. • Each node can be represented as sum-of-products (or product-of-sums). • Provides multi-level structure, but functions in the network need not correspond to logic gates.

9. Boolean network example primary outputs out1 = k2 + x2’ out2 = k3 + x1 k2 = x1’ x2 x4 + k1 k3 = k1 x4’ k1 = x2 + x3 primary inputs x1 x2 x3 x4

10. Terms • Support: set of variables used by a function. • Transitive fanout: all the primary outputs and intermediate variables of a function. • Transitive fanin: all the primary inputs and intermediate variables used by a function. Transistive fanin determines a cone of logic. cone primary inputs output

11. Technology-independent logic optimization • Simplification rewrites node to simplify its form. • Network restructuring introduces new nodes for common factors, collapses several nodes into one new node. • Delay restructuring changes factorization to reduce path length.

12. Cost in the Boolean network • Don’t know exact gate structure, but can estimate final network cost: • area estimated by number of literals (true or complement forms of variables); • delay estimated by path length.

13. Partially-specified functions • Don’t-cares can be implemented in either the on-set or off-set. • Don’t-cares provide the greatest opportunities for minimization in many cases.

14. Partially-specified function example x2 1 don’t care x1 0 1 1 x3

15. Don’t-cares in Boolean networks • In two-level function, don’t-cares are defined at primary output. • In Boolean network, structure of network itself introduces don’t-cares. • Types of structural don’t-cares: • satisfiability; • observability.

16. Satisfiability don’t-cares • Occur when an intermediate variable value is inconsistent with its function inputs. Since this can’t happen, we don’t care. f=yc y == g a=b=0, f=1 can’t happen Don’t-care for f: y’g + yg’ y g=ab a b c

17. Observability don’t-cares • Occur when an intermediate variable’s value doesn’t affect the network primary outputs. If a=1, then b is don’t-care a x b

18. Optimizations • Simplification. • Changing the way a function is represented. • Network restructuring. • Adding and removing nodes. • Delay restructuring. • Optimizations that reduce the height of critical paths.

19. Cube representation • On-set, off-set, don’t-care set, cover: x2 x1 x3

20. x2 x1 x3 Espresso example

21. Partial collapsing f1 f4 F f4 f2 f3 f3 before after

22. Factorization • Based on division: • formulate candidate divisor; • test how it divides into the function; • if g = f/c, we can use c as an intermediate function for f. • Algebraic division: don’t take into account Boolean simplification. Less expensive then Boolean division.

23. Factorization using division • Three steps: • generate potential common factors and compute literal savings if used; • choose factors to substitute into network; • restructure the network to use the new factors. • Algebraic/Boolean divison can be used to implement first step.

24. Technology mapping • Cover the function:

25. FPGA tech mapping • Cost (number of inputs) doesn’t always increase with added functions:

26. FPGAs vs. custom logic • Cost metric for static gates is literal: • ax + bx’ has four literals, requires 8 transistors. • Cost metric for FPGAs is logic element: • All functions that fit in an LE have the same cost.

27. LUT-based logic synthesis • Find the largest logic cone that will fit into the LUT: r = q + s’ s = d’ q = g’ + h d = a + b

28. Placement and routing • Two critical phases of layout design: • placement of components on the chip; • routing of wires between components. • Placement and routing interact, but separating layout design into phases helps us understand the problem and find good solutions.

29. Placement metrics • Quality metrics for layout: • area; • delay. • Area and delay determined partly by wiring. • How do we judge a placement without wiring? Estimate wire length without actually performing routing. • Design time may be important for FPGAs

30. Wire length as a quality metric bad placement good placement

31. Euclidean Manhattan Wire length measures • Estimate wire length by distance between components. • Possible distance measures: • Euclidean distance (sqrt(x2 + y2)); • Manhattan distance (x + y). • Multi-point nets must be broken up into trees for good estimates.

32. Wiring trees Steiner point

33. Placement techniques • Can construct an initial solution, improve an existing solution. • Pairwise interchange is a simple improvement metric: • Interchange a pair, keep the swap if it helps wire length. • Heuristic determines which two components to swap.

34. Placement by partitioning • Works well for components of fairly uniform size. • Partition netlist to minimize total wire length using min-cut criterion. • Partitioning may be interpreted as 1-D or 2-D layout.

35. Recursive partitioning

36. 1 net 3 nets Min-cut bisecting partitioning B A C D partition 1 partition 2

37. Min-cut bisecting partitioning, cont’d • Swapping A and B: • B drags 1 net; • A drags 3 nets; • total cut increase: 3 nets. • Conclusion: probably not a good swap, but must be compared with other pairs.

38. Kernighan-Lin algorithm • Compute min cut criterion: • count total net cut change. • Algorithm exchanges sets of nodes to perform hill-climbing—finding improvements where no single swap will improve the cut. • Recursively subdivide to determine placement detail.

39. Simulated annealing • Powerful but CPU-intensive optimization technique. • Analogy to annealing of metals: • temperature determines probability of a component jumping position; • probabilistically accept moves. • start at high temperature, cool to lower temperature to try to reach good placement.

40. Routing • Major phases in routing: • global routing assigns nets to routing areas; • detailed routing designs the routing areas. • Net ordering is a major problem. Order in whch nets are routed determines quality fo result. Net ordering is a heuristic.

41. Global routing • Choose a sequence of channels. • Not tracks within a channel. • Must take capacity into account. • Channel graph allows path algorithms to be used for global routing.

42. switch box channel channel switch box switch box channel channel channel switch box switch box switch box channel channel channel switch box channel switch box channel switch box Channel graph LE LE channel channel LE LE

43. Maze routing • Will find shortest path for a single wire, if such a path exists. • Two phases: • Label nodes with distance, radiating from source. • Use distances to trace from sink to source, choosing a path that always decreases distance to source.

44. Lee (wavefront) router

45. FPGA issues • Often want a fast answer. May be willing to accept lower quality result for less place/route time. • May be interested in knowing wirability without needing the final configuration. • Fast placement: constructive placement, iterative improvement through simulated annealing.

46. FPGA routing • Finding a route into given interconnection network. • Global routing assigns to channels. • Local routing selects the programming points used to make the connections.

47. FPGA routing techniques • Nair: route based on congestion, not distance. Route in two passes: • Estimate congestion. • Final routing. • Triptych: more gradual penalty for congestion.