An ILP-based Automatic Bus Planner for Dense PCBs

1. An ILP-based Automatic Bus Planner for Dense PCBs P. C. Wu, Q. Ma and M. D. F. Wong Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign ASPDAC 2013

2. Outline • Introduction • Problem Formulation • Methodology • Candidate routes generation • Layer assignment • Resolving congestions • Postprocessing • Experimental Results • Conclusions

3. Introduction • Nowadays, a dense PCB contains thousands of pins. • High pin density makes manual design of PCBs an extremely time consuming task. • An auto-router for PCBs would improve design productivity tremendously since each board takes about 2 months to route manually. • Design automation of PCB routing becomes a necessity.

4. Introduction • Bus planning: simultaneously solve the bus decomposition, escape routing, layer assignment and global bus routing.

5. Introduction • If the escape directions of the buses are predetermined and bus 3 is decided to escape to the left boundary, the set of buses can no longer be routed on one layer.

6. Problem Formulation • The route of a bus is composed of the escape route part and the global route part. • If the escape routes of two buses conflict, we call it internal conflict. • If the global routes of two buses conflict, we call it external conflict. • The buses conflicting with each other have to be assigned to different layers.

7. Problem Formulation • Input: • A number of components • A set of buses • The number of available routing layers • Objective: • Decide the bus escape routes and decomposition (if necessary) within the components • The global routes outside the components • The layer assignment of the topological routes of buses

8. Methodology • Candidate route generation • Escape routing and bus decomposition • Global routing • Layer assignment • ILP formulation • Resolving congestion • Postprocessing

9. Methodology

10. Candidate Routes Generation • Generate a collection of escape routes for all buses. • A global router is applied to generate the global routes. • With a number of options for escape routes and global routes, a bus may have more than one candidate route.

11. Candidate Routes Generation • Escape Routing and Bus Decomposition • The boundary that a pin cluster escapes to is called escaping boundary. • A bus has two pin clusters, it has 4X4=16 combinations of escaping boundary.

12. Candidate Routes Generation • Escape Routing and Bus Decomposition • If a bus fails to be escaped, then the bus is unable to be escaped on one layer and thus has to be decomposed into two or smaller buses. • Decompose a bus by iteratively applying the escape router until all pins are escaped. • For each bus, all of its candidate escape routes can be obtained by enumerating all the combinations of the escaping boundaries and rectilinear regions.

13. Candidate Routes Generation • Global Routing

14. Candidate Routes Generation • Global Routing

15. Candidate Routes Generation • Global Routing

16. Layer Assignment • ILP Formulation • Input: • A set of buses {b1, …, bm} • A set of candidate routes {c1, …, cn} • p routing layers • Output: • A conflict free layer assignment

17. Layer Assignment • Objective: • nci: the number of the nets of a candidate route ci • xil: candidate route ci assigned to layer l

18. Layer Assignment • Candidate Constraints: • Conflict Constraints:

19. Layer Assignment • Bus Decomposition Constraints: • Suppose b1 contains two bus decompositions, d1 and d2, where d1={b2, b3, b4} and d2 ={b5, b6}. • Only one bus decomposition can be selected by the ILP.

20. Layer Assignment • Algorithm

21. Resolving Congestions • Critical Cuts • The line segments connecting each component corner to all its visible component corners or board boundaries.

22. Resolving Congestions

23. Postprocessing • Improve the results by trying to reassign the unassigned buses to the routing layers. • Collect the set of all unassigned buses, try to reassign them to the first layer. • An ILP is formulated and solved. • Try to put the new set of unassigned buses to the second layer. • Such procedure is performed iteratively until no further improvement can be gained.

24. Experimental Results

25. Conclusions • This paper presented an automatic bus planner, including bus decomposition, escape routing, global routing and layer assignment. • The proposed planner is able to successfully route 97.4% of the nets within 2.5 hours.