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Combining Decomposition and Unfolding for STG Synthesis (application paper)

Combining Decomposition and Unfolding for STG Synthesis (application paper). Victor Khomenko 1 and Mark Schaefer 2 1 School of Computing Science, Newcastle University, UK 2 Institute of Computer Science, University of Augsburg, Germany. Asynchronous circuits.

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Combining Decomposition and Unfolding for STG Synthesis (application paper)

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  1. Combining Decomposition and Unfolding for STG Synthesis(application paper) Victor Khomenko1 and Mark Schaefer2 1School of Computing Science, Newcastle University, UK 2Institute of Computer Science, University of Augsburg, Germany

  2. Asynchronous circuits • The traditional synchronous (clocked) designs lack flexibility to cope with contemporary design technology challenges Asynchronous circuits – no clocks: • Low power consumption and EMI • Tolerant of voltage, temperature and manufacturing process variations • Modularity – no problems with the clock skew and related subtle issues [ITRS’05]: 22% of designs will be driven by ‘handshake clocking’ in 2013, and 40% in 2020 • Hard to synthesize efficient circuits • The theory is not sufficiently developed • Limited tool support

  3. Syntax-directed translation Idea: Convert the specification to a network of standard handshake components (Balsa, Tangram) • Computationally efficient • Solution is guaranteed • Produces highly over-encoded circuits, with large area and low performance

  4. Logic synthesis Idea: Synthesize the circuit by exploring the state space of the specification • Produces good circuits • Solution is not guaranteed • State space explosion: synthesis based on state graphs is feasible only for small specifications (20-30 signals for BDD-based Petrify)

  5. Unfoldings • Alleviate the state space explosion problem • More visual than state graphs • Proven efficient for model checking • Can often synthesize specifications with 100-200 signals • Still not enough for real-life designs!

  6. Decomposition Idea: • Decompose the control path of the specification into smaller clusters and synthesize them one-by-one • Use syntax-directed translation for clusters on which synthesis fails • Can halve the area of the control path and improve its latency [Carmona, Cortadella DAC’06]

  7. Data Transceiver Device Bus d lds dsr VME Bus Controller ldtack dtack dtack- dsr+ lds+ d- lds- ldtack- ldtack+ dsr- dtack+ d+ Example: VME Bus Controller

  8. dtack- dsr+ lds+ d- lds- ldtack- ldtack+ dsr- dtack+ d+ lds lds: dsr, ldtack, d dsr ldtack d: ldtack, dsr dtack: d d dtack Initial partition Include signal triggers and choices: • lds: dsr, ldtack, d • d: ldtack, dsr • dtack: d

  9. dtack- dtack- dtack- dsr+ dsr+ dsr+ lds+ lds+ lds+ d- d- d- lds- lds- lds- ldtack- ldtack- ldtack- ldtack+ ldtack+ ldtack+ dsr- dsr- dsr- dtack+ dtack+ dtack+ d+ d+ d+ Initial decomposition

  10. dsr+ lds+ dtack- d- lds- ldtack- ldtack+ d- dsr- d+ dtack+ d+ lds d Irreducible CSC conflict dsr+ dsr+ lds+ d- d- ldtack- ldtack- ldtack+ ldtack+ dsr- dsr- d+ d+ Transition contraction Merge similar components

  11. dsr+ lds+ d- lds- ldtack- ldtack+ dsr- d+ e8 dsr+ e1 e2 e3 e4 e5 e7 e11 lds+ dsr+ lds+ ldtack+ d+ dsr- d- lds- ldtack- e10 e9 Resolving CSC conflicts

  12. Resolving CSC conflicts (cont’d) dsr+ lds+ csc+ d- lds- ldtack- ldtack+ csc- dsr- d+

  13. Resulting Circuit Data Transceiver Device Bus d lds dtack dsr csc ldtack

  14. Implementation Large STGs(specification) structural (approximate) tests DESIJ decomposition unfolding-based (exact) tests Medium STGs PUNF decomposition MPSAT Small STGs(components)‏ synthesis

  15. t t Safeness-preserving contractions • Unfolding is more efficient for safe nets • Decomposition can create unsafe nets • Contractions have to preserve safeness t Example Structural condition

  16. Auto-conflicts • Auto-conflicts appear if too many signals wereremoved • Backtracking reinserts signals which remove the auto-conflict • Unnecessary backtracking increases thefinal components a+ a+

  17. Implicit places • Implicit places are places the absence of tokens in which can never be the sole reason for some transition to be disabled • Such places can be deleted without changing the behaviour of the STG • Removing such places is essential for decomposition, because they can • cause false alarms for other tests • prevent contractions • Structural test looks for a subset of implicit places (redundant places, shortcut places)

  18. Experimental results • Large trees composed of alternating levels of sequencers and parallelisers were considered • Intractable for stand-alone MPSAT and Petrify

  19. Experimental results

  20. Experimental results • Outperforms stand-alone MPSAT and Petrify on large STGs • Some intractable for stand-alone MPSAT and Petrify benchmarks were easily synthesized • Huge STGs can be synthesized, e.g. SeqParTree-10 with 12598 places, 8188 transitions, and 1025 inputs and 3069 outputs was synthesized in less then 70 minutes

  21. Thank you! Any questions?

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