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Pixel : LS1, Run2 and Fase 2

Pixel : LS1, Run2 and Fase 2. Slides per Clara 17 September 2014 G. Darbo– INFN / Genova Indico agenda: https ://agenda.infn.it/conferenceDisplay.py?confId= 8420. 2014 Activities – 2015 Plan. 2014: CSN1 funded (Feb and May) R&D Phase 2 activities for ATLAS & CMS inner trackers.

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Pixel : LS1, Run2 and Fase 2

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  1. Pixel : LS1, Run2 and Fase 2 Slides per Clara 17 September 2014 G. Darbo– INFN / Genova Indico agenda: https://agenda.infn.it/conferenceDisplay.py?confId=8420

  2. 2014 Activities – 2015 Plan • 2014: CSN1 funded (Feb and May) R&D Phase 2 activities for ATLAS & CMS inner trackers. • Development of 3D and Active Edge sensors with FBK – 3 Batches (ATLAS/CMS) • Bump-bonding: development of Indium bumps (6” sensors) and produce modules • Develop a technology for pixel detector hybridization using C (dielectric) instead of R (bump-bonding) coupling • Completion of CO2 test plant (combined ATLAS / LHCb) • 2015: Activities and line of funding • Continue with 3D Sensor plan: produce modules, test in lab and TB, irradiate, procure sensors for next FBK run. • Bump-bonding: for testing FBK sensors and to develop for future RD53 requirements • CO2 cooling: contribute to ATLAS stave R&D, thermal simulation and test with CO2 plant • Multi-module R/O: use leading experience of ROD designer (BO) to develop a 16 module table-top road for architecture study and for test-beam application. • Upgrade to USBPix3: most diffused single module system based on USB. Upgrade also for use if HV/HR-CMOS • HV/HR-CMOS: presented a new project in CSN5 (BO, GE, MI)

  3. 3D Sensor Program - 2014 Planned 3 run at FBK in 2014 – Funded by CSN1 in Feb • No.1: DRIE process setting up for thin columns. Process in completion. Found that 5-6 µm are the best suitable column diameter. • No.2: test planar process with SiSi DWB and Epi substrates. Layout completed, mask submission, wafer expected in 6 weeks. • No.3: 3D single side process with SiSi DWB and Episubstrates. Layout in discussion. Compatible layout with other foundries (CNM) to simplify common test of devices. Note: • A second 3D run is foreseen at the end of 2015 / early 2016 – layout matching RD-53 layout. Schedule presented in Feb’14. Still up to date. Need approval from MEMS3 committee of 3rd batch!

  4. FBK: Status of Batches • Batch 1: study of columns In measurement • Batch 2: study SiSisubtrates Mask submitted 3.8 um 158 um 5.6 um ATLAS CMS • Batch 3: 3D sensors Layout study and Simulation of a 3D pixel cell Test structures for Si-Si qualification

  5. CCPD Hybridization Process Recipe Spin SU-8 photoresist Pattern pillars by mask Spacer define the distance between chips Target to D = 5 µm, C ~ 4 fF for 18 µm pad diameter. Proper qualified glue • HV/HR-CMOS chip coupled capacitively to R/O chip (CCPD – Capacitively Coupled Pixel Detector) instead of “classic” bump-bonding • Develop a technique to insert uniform, well defined thickness of dielectric between R/O and HV/HR-CMOS chips • Should be a cost effective, rad-hard process to transfer to industry • Test program in progress: • See preliminary results next slide • Activities will continue in the HVR_CCPD project in CSN5 (new experiment) • Involving BO, GE & MI • Also scientists outside ATLAS will participate. R/O CHIP R/O CHIP R/O CHIP DETECTOR CHIP Glue deposition Align & pressure

  6. Deposition of Pillars (spacers) 2-inch mask below with different Densities of spacers – FE-I4/FE-I3 Structures. SU8-2005 deposited on 2-inch wafer from Siegert Credits: V. Ceriale FE-I4 with matrix of SU8 spacers: 200 µm x 200 µm columns 4.7 µm high FE-I4 with matrix of SU8 spacers: 40 µm x 40 µm columns 4.7 µm high

  7. 2014 - CO2 Cooling Plant Attilio…

  8. Milestones

  9. Spare slides

  10. 3D Sensors – Proposed Process Single side 3D process New generation of 3D sensors • 6” wafer new process at FBK • Smaller pixel (event pileup) • reduce column distance (2x1016neq/cm2) • Thinner pixel (≤1.5ke threshold) • TCAD simulation: Optimal Q, Lower Cdet ,… • Bias voltage applied to back side (as IBL) Single side 3D process on: • Si-Si DWB (Direct Wafer Bonding) • Epitaxial wafers n++ col Charge Amp. Bump-bond P+Epi layer / P+ High Ω•cm wafer 100÷150µm Epi – SiSi DWB P++ Low Ω•cm wafer Thin-down -Vb metal p++ col • TCAD capacitance simulation • Layout: 2 n-columns in 25x150 µm2 • Total capacitance for dcol=5µm • 100 µm thick  71 fF/pix • 150 µm thick  88 fF/pix • It was 200 fF/pix for IBL

  11. DRIE for Ohmic Columns 3.8 um 158 um 5.6 um 7.6 um

  12. DRIE for Junction Columns LEFT CENTER RIGHT

  13. Planar test batch ATLAS CMS • p-typeSiSi DWB wafersfrom ICEMOS • 100-mm and 130-mm HR activesensorthickness • p-spray & p-stop isolation • Layout ready, masksordered • To start now, to be completedin 6-7 weeks Test structures for Si-Si qualification

  14. Wafers Sets – To Bump-Bond 3D Double Side Batch Planar ATLAS/CMS “Batch 2” CMS Single chip (24x) (1E, 2E, 3E, 4E) • In program 4 sensor batches that would need BB in 2014/15: • 3D double side – October - Funds (MI) assigned for 2014 • Planar ATLAS/CMS Batch 2 – November – Funds (FI/PI) assigned 2014 • 3D and Active edge batches coming 2015 – no funds yet. In 2015 request ATLAS FE-I4 (13x) ATLAS CMS CMS Quads (6x) (2E, 3E) MEDIPIX2 (4x) NA62 test chip (20x) Test structures for Si-Si qualification

  15. SU8-2005 Results Profile scan direction • 1.26 µm of bow. Column highs are very uniform: 4.7 µm over 2 cm • Results obtained with a spinning rotation of 2500 rpm and SU8-2005

  16. Future Plan: M-Module R/O • Le caratteristichedellaschedasono: • Completacompatibilità firmware e software con il ROD/BOC IBL ROD/BOC in one card • Possibilità di operaresenzacrate (table-top) • Connessioneottica o elettrica di 16 FE-I4 • Possibilità di connessioneesterna via GbitETH, S-Link (Modalitàcompatibile con FW/SW IBL) • Possibilità di utilizzo per test GBT/FELIX, con uscitaPCIe e protocolliInfiniband, rapid-io, 40-100 GBe • Costi: • Prototipaggio e fabbricazione di due schede10 k€ • Realizzazione di 5 schede per ilaboratoriitaliani15 k€ • Componenti off-shelf per ilsistema10 k€ Attività BO-GE Prototipi 2015 Produzione 5 schede 2016

  17. Got Funded • 3D • Funded 3 batches at FBK: • Mechanical test – approved by MEMS3 committee – order placed (3x2200 €) • Simple planar to qualify substrates – approved by MEMS3 – order placed (6x2200 €) • 3D batch, single side, on hold waiting batch 2. • Substrates • Ordered 55 wafers from IceMOS (SiSi wafer bonded) – material is on shipment • Looking for Epi wafers – indirect contact with SHINETSU – offer received (25 wafers – 11.9 kCHF) – doubts on specifications (epi-layer thickness spread: 104÷156 µm!) • Bump-bonding • Funded 20 k€ for BB at Selex + 7 k€ for FE-I4B • Bump-bond 3D sensors in production at FBK – old design IBL-like • Develop In-bumps for high density – incomplete funding (cut the dummy wafers). • HV-CMOS hybridization • FE-I4B plus consumables to test hybridization • CO2 cooling • Funded TRACI CO2 cooler

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