High-Rate Level-1 Trigger Design Proposal for the CBM Experiment

1. High-Rate Level-1 Trigger Design Proposalfor the CBM Experiment Ivan Kisel for Kirchhoff Institute of Physics, Uni-Heidelberg, Germany Laboratory of Information Technologies, JINR, Dubna, Russia • Level-1 Trigger: • Concept • Prototype • Simulation • Reconstruction Ivan Kisel JINR-GSI meeting

2. Objectives We propose the development of a generic, modular, high rate, high throughput, reliable commodity compute farm infrastructure and prototype for the specific requirements of the CBM experiment. The scalability is demonstrated by appropriate simulations. The prototype farm is to be subjected to regular use by the collaboration for simulation in parallel to the real-time on-line performance testing and monitoring. • High performance farm test bed • Test most of aspects of the system using detector mock-ups. • MHz cluster resource management • Resource management, scheduling algorithm and infrastructure. • MHz reliable low-cost networking framework (ATOLL, SCI,Infiniband, …) • At least two NIC candidates are planned to be evaluated. At least one NIC will then be implemented in the prototype. • Cluster fault tolerance framework • Automatic remedy to most error conditions without human intervention or isolation and documentation for irreparable errors. • MHz cluster simulation • Test all possible operating aspects as well as scalability of the system. • Level-1 reconstruction algorithm • High speed algorithm for triggering. • FPGA co-processor framework • FPGA co-processor will implement bus snooping techniques. Ivan Kisel JINR-GSI meeting

3. L1 L2 DAQ Localprocessing Sub-eventbuilding Eventprocessing ReactionCounter TRD Trackletsearch L1 TMU L2 Algorithm RICH Clustersearch Ring search IT Clustersearch IT-VertexProcessor TOF Readout HLT / DAQ Sketch of Data Flow and Data Topology Ivan Kisel JINR-GSI meeting

4. 3D Topology PC Farm TagNet Input Data Sch TRD TRD RU RICH RICH RU IT IT RU z TOF TOF x RU y Ivan Kisel JINR-GSI meeting

5. CPU FPGA A Compute Node • ATOLL • SCI • Infiniband • … NIC In Out PCI bus Ivan Kisel JINR-GSI meeting

6. Level-1 Trigger Prototype in Heidelberg 32 dual CN 1 Gb/s Ethernet 6 Gb/s 2D SCI 2D torus >1 MHz 480 MB/s p-p 450 MB/s x-y Ivan Kisel JINR-GSI meeting

7. GUI of Prototype • Automatic setup of the compute farm • Configure and control processes on every CN Ivan Kisel JINR-GSI meeting

8. Hardware Initiated DMA Transfer Ivan Kisel JINR-GSI meeting

9. Ptolemy II Simulation of the Trigger Ivan Kisel JINR-GSI meeting

10. TRACK RECONSTRUCTION based on the Cellular Automaton Method XZ (bending) / YZ (non-bending) Ivan Kisel JINR-GSI meeting

11. ALL MC TRACKS RECONSTRUCTABLE TRACKS Number of hits >= 3 REFERENCE TRACKS Momentum > 1 GeV TRACKING EFFICIENCY RECO STATISTICS100 events Refprim efficiency : 98.36 | 46562 Refset efficiency : 94.85| 49250 Allset efficiency : 90.09 | 64860 Extra efficiency : 77.79 | 15610 Clone probability: 0.11| 74 Ghost probability : 5.18| 3358 Reco MC tracks/event: 648 Timing/event : 175 ms CA – INTRINSICALLY LOCAL AND PARALLEL TIMING (ms) Fetch ROOT MC data 63.3 Copy to local arrays and sort 12.4 Create and link segments115.7 Create track candidates53.5 Select tracks2.6 FPGA Co-processor 98% CPU 2% Ivan Kisel JINR-GSI meeting

12. Plans: Kirchhoff Institute of Physics, Uni-Heidelberg, Germany Laboratory of Information Technologies, JINR, Dubna, Russia • Develop Architecture with 3D topology and TagNet. • Heidelberg (3) • Develop Scheduler. • Heidelberg (1) • Investigate the Prototype of 32 dual CNs at > 1 MHz. • Heidelberg (2) • Advance the Simulation based on the prototype measurements. • Dubna (2) • Investigate different Network Interface Cards applicability. • Heidelberg (3) + Dubna (2) • Develop the Reconstruction algorithm. • Heidelberg (1) + Dubna (4) Ivan Kisel JINR-GSI meeting