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Design of a Near Threshold Low Power DLL for Multiphase Clock Generation and Frequency Multiplication. Mehdi Sadi , Italo Armenti. Outline. Introduction and Motivation Background Our Works and simulations Conclusions and Future Works. Introduction and Motivation.
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Design of a Near Threshold Low Power DLL for Multiphase Clock Generation and Frequency Multiplication MehdiSadi, ItaloArmenti
Outline • Introduction and Motivation • Background • Our Works and simulations • Conclusions and Future Works
Introduction and Motivation • Delay Locked Loops (DLL) are extensively used for multiphase clock generation in SoC and in clock and data recovery circuits. • DLL`s counterpart Phase Locked Loops(PLL) suffer from instability due to PVT variation and noise. • Very few researchers have looked into the effect of voltage scaling on DLL performance .
Design Challenges Design challenges when voltage supply is scaled down • Appropriate device sizes in the critical path, • Ensuring correct duty cycle at output frequency. • Keeping static phase error within bounds.
Background (Mesgardazeh et. al) • Possible to redesign with reduced components but same performance at operating frequency.
Phase Detector • C2MOS DFF with Reset option. • Critical path devices are sized to ensure faster charging and discharging at the desired frequency range.
Delay Line • Binary weighted switched capacitors control the delay per stage.
Delay Line Design ** • Delay per stage, • At lock in condition The switching voltage should be adjusted at VDD/2 to avoid duty cycle error.
Counter • 8 bit binary up down counter with reset and hold options. • The counter is power and clock gated to reduce power when the clock phases are aligned. • During Sleep mode the counting states are held in a latch. Gating Effect Started Power without gating = 9.1uW Power with gating = 2.72 uW 70 % Power saved with gating
Edge Combiner • XOR Gate Based Edge Combiner. Generates 4 times the reference frequency • To ensure proper duty cycle the Devices in the critical path must be sized properly. Sizing also depends on operating frequency range.
Conclusion • We have designed a ultra low power all digital DLL operating at 80 -200MHz with 0.7V supply and 120uW. • The DLL can be scaled down to operate at further low voltage by adjusting the critical path device widths