V123S Event Link Encoder, Transmission System and PLL Receiver

1. V123S Event Link Encoder, Transmission System and PLL Receiver Thomas M. Kerner (BNL) SNS Global Controls SNS Software Final Design Review

2. Event Link System Features • Low Latency Event Delivery using short code length, 17MHz carrier, passive fanouts and short code lengths. • Asynchronous 12-bit encode and decode with hardware prioritization to allow fast event delivery. High priority events will transmit first. Trigger priority runs from left to right on input modules. • Hybrid optical and shielded twisted wire pair system • 1 ns Jitter Clock Recovery using PLL receiver • Low Bit Error Rate with high signal to noise ratio • Single Cable Clock and Data eliminates clock skew and reduces cable cost • 256 Event Codes with priority translation table so new priorities may be assigned to event codes without affecting receivers. SNS Software Final Design Review

3. Event Link System Features (cont.) • Beam Synchronous Event Link carrier is a multiple of the RF clock • Free PLL receiver drop-in artwork, parts list and program file available to DOE facilities for the PLL Link Receiver Interface. • Lock out of low priority events including the message stack between pre-pulse PP and TEXT to avoid delaying the extraction event. • A linked series of events with programmable delays may be generated by feeding back outputs to inputs. • Message FIFO for software generated events. • Tracks with LLRF for machine tune an energy changes SNS Software Final Design Review

4. Provides: • Facility-wide broadcast event timing, LLRF synchronous clock, and informational events for distributed systems: • Neutron chopper • LINAC chopper • LINAC and Ring RF • Injection and Extraction • Beam Instrumentation • Scopes • Utility Modules SNS Software Final Design Review

5. CONTROL Interrupt enable On-line/Off-line Interrupt ROAK/RORA Automatic clock switching on LLRF status (between internal / external LLRF) Manual clock override Interrupt vector register Interrupt level register Event FIFO input register STATUS VME ID string RF clock bad (occ.) Beam clock fault (r.t.) FIFO full (r.t. & occ.) FIFO empty (r.t.) Clock in-use (r.t.) PP – Text lockout (r.t.) Input error registers (occ.) FIFO Value < 64 error V101 Input module > 63 error Input rate error, lost event Status & Control Registers For details see V123S Event Link Module manual at http://www.sns.bnl.gov/epics/timing/doc/v123s/V123S revA1.htm SNS Software Final Design Review

6. Event Link System - Block Diagram SNS Software Final Design Review

7. Event Link System - Block Diagram SNS Software Final Design Review

8. Event Link Encoder & Input Module SNS Software Final Design Review

9. Event Link Encoder – P2 Dedicated Bus Encoded Beam Sync output 64 External Inputs 32x FREV Clock Beam Sync Encoder Event Input Module Event Input Module Event Input Module Event Input Module P2 P2 P2 P2 P2 VME BUS Private P2 bus SNS Software Final Design Review

10. Event Link Encoder - Bi Phase Mark Encoding SNS Software Final Design Review

11. PLL Receiver – IP Module • Insert IP module Prototype Picture Here SNS Software Final Design Review

12. Fanout & Fiberoptic Chassis 16 outputs on production units Fiber optic receiver module Fiber optic transmitter module Power supplies SNS Software Final Design Review

13. Machine Cycle & Accumulation Detail SNS Software Final Design Review