332:437 Lecture 26 IEEE Boundary Scan Standard & System Test

1. 332:437 Lecture 26 IEEE Boundary Scan Standard & System Test • Boundary Scan Standard • Purpose • Pin electronics • Instructions • System test • Methods • System-on-a-Chip (SoC) testing • Summary Material from Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, by M.L. Bushnell and V. D. Agrawal, Boston: Kluwer Academic Publishers, 2000 Bushnell: Digital Systems Design Lecture 26

2. IEEE 1149.1 Boundary Scan Standard Bushnell: Digital Systems Design Lecture 26

3. Motivation for Standard • Bed-of-nails printed circuit board (PCB) tester gone • We put components on both sides of PCB & replaced Dual In-line Packagess with flat packs to reduce inductance • Nails would hit components • Reduced spacing between PCB wires • Nails would short the wires • PCB Tester must be replaced with built-in test delivery system -- JTAG does that • Need standard System Test Port and Bus • Integrate components from different vendors • Test bus identical for various components • One chip has test hardware for other chips Bushnell: Digital Systems Design Lecture 26

4. Purpose of Standard • Lets test instructions and test data be serially fed into a component-under-test (CUT) • Allows reading out of test results • Allows RUNBIST command as an instruction • Too many shifts to shift in external tests • JTAG can operate at chip, PCB, & system levels • Allows control of tri-state signals during testing • Lets other chips collect responses from CUT • Lets system interconnect be tested separately from components • Lets components be tested separately from wires Bushnell: Digital Systems Design Lecture 26

5. System Test Logic Bushnell: Digital Systems Design Lecture 26

6. Instruction Register Loading with JTAG Bushnell: Digital Systems Design Lecture 26

7. System View of Interconnect Bushnell: Digital Systems Design Lecture 26

8. Boundary Scan Chain View Bushnell: Digital Systems Design Lecture 26

9. Elementary Boundary Scan Cell Bushnell: Digital Systems Design Lecture 26

10. Serial Board / MCM Scan Bushnell: Digital Systems Design Lecture 26

11. Parallel Board / MCM Scan Bushnell: Digital Systems Design Lecture 26

12. Tap Controller Signals • Test Access Port (TAP) includes these signals: • Test Clock Input(TCK) -- Clock for test logic • Can run at different rate from system clock • Test Mode Select(TMS) -- Switches system from functional to test mode • Test Data Input(TDI) -- Accepts serial test data and instructions -- used to shift in vectors or one of many test instructions • Test Data Output(TDO) -- Serially shifts out test results captured in boundary scan chain (or device ID or other internal registers) • Test Reset(TRST) -- Optional asynchronous TAP controller reset Bushnell: Digital Systems Design Lecture 26

13. SAMPLE / PRELOAD Instruction -- SAMPLE Purpose: Get snapshot of normal chip output signals Put data on bound. scan chain before next instr. Bushnell: Digital Systems Design Lecture 26

14. SAMPLE / PRELOAD Instruction -- PRELOAD Bushnell: Digital Systems Design Lecture 26

15. EXTEST Instruction • Purpose: Test off-chip circuits and board-level interconnections Bushnell: Digital Systems Design Lecture 26

16. INTEST Instruction • Purpose: • Shifts external test patterns onto component • External tester shifts component responses out Bushnell: Digital Systems Design Lecture 26

17. RUNBIST Instruction • Purpose: Allows you to issue BIST command to component through JTAG hardware • Optional instruction • Lets test logic control state of output pins • Can be determined by pin boundary scan cell • Can be forced into high impedance state • BIST result (success or failure) can be left in boundary scan cell or internal cell • Shift out through boundary scan chain • May leave chip pins in an indeterminate state (reset required before normal operation resumes) Bushnell: Digital Systems Design Lecture 26

18. CLAMP Instruction • Purpose: Forces component output signals to be driven by boundary-scan register • Bypasses the boundary scan chain by using the one-bit Bypass Register • Optional instruction • May have to add RESET hardware to control on-chip logic so that it does not get damaged (by shorting 0’s and 1’s onto an internal bus, etc.) Bushnell: Digital Systems Design Lecture 26

19. IDCODE Instruction • Purpose: Connects the component device identification register serially between TDI and TDO • In the Shift-DR TAP controller state • Allows board-level test controller or external tester to read out component ID • Required whenever a JEDEC identification register is included in the design Bushnell: Digital Systems Design Lecture 26

20. MSB LSB 31 28 Version (4 bits) 27 12 Part Number (16 bits) 11 1 Manufacturer Identity (11 bits) 0 ‘1’ (1 bit) Device ID Register --JEDEC Code Bushnell: Digital Systems Design Lecture 26

21. USERCODE Instruction • Purpose: Intended for user-programmable components (FPGA’s, EEPROMs, etc.) • Allows external tester to determine user programming of component • Selects the device identification register as serially connected between TDI and TDO • User-programmable ID code loaded into device identification register • On rising TCK edge • Switches component test hardware to its system function • Required when Device ID register included on user-programmable component Bushnell: Digital Systems Design Lecture 26

22. HIGHZ Instruction • Purpose: Puts all component output pin signals into high-impedance state • Control chip logic to avoid damage in this mode • May have to reset component after HIGHZ runs • Optional instruction Bushnell: Digital Systems Design Lecture 26

23. BYPASS Instruction • Purpose: Bypasses scan chain with 1-bit register Bushnell: Digital Systems Design Lecture 26

24. Summary • Boundary Scan Standard has become absolutely essential -- • No longer possible to test printed circuit boards with bed-of-nails tester • Not possible to test multi-chip modules at all without it • Supports BIST, external testing with Automatic Test Equipment, and boundary scan chain reconfiguration as BIST pattern generator and response compacter • Now getting widespread usage Bushnell: Digital Systems Design Lecture 26

25. System Test Bushnell: Digital Systems Design Lecture 26

26. A System and Its Testing • A system is an organization of components (hardware/software parts and subsystems) with capability to perform useful functions. • Functional test verifies integrity of system: • Checks for presence and sanity of subsystems • Checks for system specifications • Executes selected (critical) functions • Diagnostic test isolates faulty part: • For field maintenance isolates lowest replaceable unit (LRU), e.g., a board, disc drive, or I/O subsystem • For shop repair isolates shop replaceable unit (SRU), e.g., a faulty chip on a board • Diagnostic resolution is the number of suspected faulty units identified by test; fewer suspects mean higher resolution Bushnell: Digital Systems Design Lecture 26

27. System Test: Partitioning for Test • Partition according to test methodology: • Logic, Memory, and Analog blocks • Provide test access: • Boundary scan • Analog test bus • Provide test-wrappers (also called collars) for cores • Core is a chip layout part • System-on-a-chip made up of multiple cores Bushnell: Digital Systems Design Lecture 26

28. Test-Wrapper for a Core • Test-wrapper (or collar) is the logic added around a core to provide test access to the embedded core. • Test-wrapper provides: • For each core input terminal • A normal mode – Core terminal driven by host chip • An external test mode – Wrapper element observes core input terminal for interconnect test • An internal test mode – Wrapper element controls state of core input terminal for testing the logic inside core • For each core output terminal • A normal mode – Host chip driven by core terminal • An external test mode – Host chip is driven by wrapper element for interconnect test • An internal test mode – Wrapper element observes core outputs for core test Bushnell: Digital Systems Design Lecture 26

29. Wrapper elements Core Functional core inputs Functional core outputs Scan chain Scan chain from/to External Test pins Scan chain to/from TAP A Test-Wrapper Wrapper test controller Bushnell: Digital Systems Design Lecture 26

30. DFT Architecture for SOC Test source Test sink User defined test access mechanism (TAM) Func. outputs Functional outputs Functional inputs Func. inputs Module 1 Module N Test Test wrapper wrapper Instruction register control Test access port (TAP) Serial instruction data TDI SOC outputs TMS TCK TDO SOC inputs TRST Bushnell: Digital Systems Design Lecture 26

31. Summary • Functional test: verify system hardware, software, function and performance; pass/fail test with limited diagnosis; high (~100%) software coverage metrics; low (~70%) structural fault coverage. • Diagnostic test: High structural coverage; high diagnostic resolution; procedures use fault dictionary or diagnostic tree. • SOC design for testability: • Partition SOC into blocks of logic, memory and analog circuitry, often on architectural boundaries. • Provide external or built-in tests for blocks. • Provide test access via boundary scan and/or analog test bus. • Develop interconnect tests and system functional tests. • Develop diagnostic procedures. Bushnell: Digital Systems Design Lecture 26

32. References • For a course on testing taught at Rutgers University, see website: http://www.caip.rutgers.edu/~bushnell/rutgers.html Bushnell: Digital Systems Design Lecture 26