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Built-in Adaptive Test and Calibration of DAC

Built-in Adaptive Test and Calibration of DAC. Wei Jiang and Vishwani D. Agrawal Electrical and Computer Engineering Auburn University, Auburn, AL 36849 18 th IEEE North Atlantic Test Workshop 2009. Outline. Overview Previous Work Proposed BIST Scheme Adaptive Self-Calibration of DAC

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Built-in Adaptive Test and Calibration of DAC

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  1. Built-in Adaptive Test and Calibration of DAC Wei Jiang and Vishwani D. Agrawal Electrical and Computer Engineering Auburn University, Auburn, AL 36849 18th IEEE North Atlantic Test Workshop 2009

  2. Outline • Overview • Previous Work • Proposed BIST Scheme • Adaptive Self-Calibration of DAC • Simulation Results • Conclusion

  3. Overview • Proposed design-for-testability (DFT) architecture for a mixed-signal SoC • Accuracy • Performance • Cost • Test of on-chip DAC and ADC • Linearity (DNL/INL) • Resolution and speed • Signal-to-noise ratio (SNR)

  4. A Typical Mixed-Signal BIST for SoC* * F. F. Dai and C. E. Stroud, “Analog and Mixed-Signal Test Architectures,” Chapter 15, p. 722 in System-on-Chip Test Architectures: Nanometer Design for Testability, Morgan Kaufmann, 2008.

  5. Previous Work W. Jiang and V.D. Agrawal, Built-In Test and Calibration of DAC/ADC Using A Low-Resolution Dithering DAC, NATW’08

  6. Non-linearity Errors Non-linearity error Non-linearity error

  7. Proposed BIST Scheme

  8. Proposed BIST Scheme (Cont.) • DSP for BIST control • Components • 1-bit first-order sigma-delta modulator • Low-pass filter (integrator or comb filter) • Adaptive polynomial evaluation/fix circuit • Low-resolution dithering DAC • Loop-back circuitry connecting internal DAC and ADC

  9. Testing and characterization of DAC

  10. Testing of DAC (Cont.) • Response and ramp input compared for INL error • INL error analyzed by adaptive polynomial fitting algorithm • Best matching polynomials selected for various and DAC profiles • Test results indicated by calculated characteristics (offset, gain and harmonic distortion, etc) • Polynomial coefficients calculated for dithering DAC to improve INL

  11. Polynomial Fitting • Introduced by Sunter et al. in ITC’97 and A. Roy et al. in ITC’02 • Summary: • Divide DAC transfer function into four sections • Combine function outputs of each section (S0, S1, S2, S3) • Calculate four coefficients (b0, b1, b2, b3) by easily-generated equations

  12. Third-Order Polynomial

  13. First- and second-order Polynomial First-order polynomial Second-order polynomial

  14. Adaptive Polynomial Fitting • Fitting INL error from lower order polynomial to higher order • Calculate RMS error of each polynomial • Select the polynomial with least RMS error (when RMS error rising with higher order polynomial)

  15. Sigma-Delta Modulator 1-bit first-order sigma-delta modulator Transfer function in z-domain

  16. Sigma-Delta Modulator (Cont.) SNR (dB) Third-order Second-order 17-bit ENOB104.1dB First-order Oversampling ratio (OSR)

  17. Dithering DAC Estimated DAC resolution (bits) Oversampling ratio (OSR) α=1 2 3 17bits Resolution of dithering-DAC (bits)

  18. Simulation of DAC Test • 14-bit DAC • 16K ramp codes • INL error up to ±1.5dB INL of 14-bit DAC (LSB) Indices of 14-bit DAC-under-test

  19. Simulation (Cont.) INL of 14-bit DAC (LSB) • Fitting results by different order polynomial Indices of 14-bit DAC-under-test

  20. Best-matching Polynomial

  21. Conclusion • A built-in self-test and self-calibration solution for mixed-signal SoC is proposed • A polynomial fitting algorithm is employed for INL error correction • Fault-tolerance levels can be chosen for various applications • Simulation results show significant improvement in linearity after calibration

  22. Q&A Thank you!

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