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SYLLABUS

SYLLABUS. Section B Real Time and Embedded Operating Systems: Introduction , Hardware Elements, Structure Interrupt Driven, Nanokernel , Microkernel and Monolithic kernel based models. Scheduling – Periodic , Aperiodic and Sporadic Tasks,

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SYLLABUS

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  1. SYLLABUS Section B • Real Time and Embedded Operating Systems: • Introduction, • Hardware Elements, • Structure • Interrupt Driven, • Nanokernel, • Microkernel and • Monolithic kernel based models. • Scheduling – • Periodic, • Aperiodic and • Sporadic Tasks, • Introduction to Energy Aware CPU Scheduling.

  2. ASSIGNMENT #1: 16 JAN 2014 SECTION B • What are the characteristics of Real Time and Embedded systems? • Describe Hardware Elements used in RE systems. • Describe structure of Real Time and Embedded (RE) operating systems clearly specifying difference between Interrupt Driven, Nanokernel, Microkernel and Monolithic kernel based models. • Differentiate between Periodic, Aperiodic and Sporadic Tasks. What algorithms are available for their scheduling? • Describe Energy Aware CPU Scheduling. SECTION A • What do you understand by Multi-Processor and Distributed (MPD) systems? Describe Architecture of Operating Systems for such systems. • How is Resource sharingand Load Balancingachieved in MPD systems? • What are the Design and Development Challenges in MPD Operating Systems? • Write short notes on: • Inter-process Communication in a typical MPD OS • Availability of resources in MPD systems. • Fault Tolerance in MPD systems • Logical Clock • Mutual Exclusion • Distributed File System

  3. ADVANCED OPERATING SYSTEMS MCA 404

  4. SYLLABUS

  5. SYLLABUS Section B • Real Time and Embedded Operating Systems: • Introduction, • Hardware Elements, • Structure • Interrupt Driven, • Nanokernel, • Microkernel and • Monolithic kernel based models. • Scheduling – • Periodic, • Aperiodic and • Sporadic Tasks, • Introduction to Energy Aware CPU Scheduling.

  6. SYLLABUS Section C • Cluster and Grid Computing: • Introduction to Cluster Computing and MOSIX OS, • Introduction to the Grid, • Grid Architecture, • Computing Platforms: • Operating Systems and Network Interfaces, • Grid Monitoring and Scheduling, • Performance Analysis, • Case Studies.

  7. SYLLABUS Section D • Cloud Computing: • Introduction to Cloud, • Cloud Building Blocks, • Cloud as IaaS, PaaS and SaaS, • Hardware and software virtualization, • Virtualization of OS • Hypervisor KVM, • SAN and • NAS back-end concepts. • Mobile Computing: • Introduction, • Design Principles, • Structure, Platform and Features of Mobile Operating Systems (Android, IOS, Windows Mobile OS).

  8. SYLLABUS References: • SibsankarHaldar, Alex A. Arvind, “Operattng Systems”, Pearson Education Inc. • Tanenbaum and Van Steen, “Distributed systems: Principles and Paradigms”, Pearson, 2007. • M. L. Liu, “Distributed Computing: Principles and Applications”, Addison Wesley, Pearson • Maozhen Li, Mark Baker, “The Grid – Core Technologies”, John Wiley & Sons 2005

  9. SECTION B

  10. SECTION B • Real Time and Embedded Operating Systems:

  11. 8051 MICROCONTROLLER

  12. 8051 MICROCONTROLLER • PDIP - Plastic Dual-in-Line Package • CERDIP - Ceramic Dual-in-Line Package

  13. 8051 SCHEMATIC DIAGRAM

  14. 8051 SCHEMATIC DIAGRAM

  15. COMPARISON OF 8051 FAMILY MEMBERS

  16. *OE: Output Enable PSEN (Pin 29). (Not used for AT89S52) • Program Store Enable. This is an output pin. In an 8031 based system, in which an external ROM holds the program code, this pin is connected to the OE* pin of ROM. • PSEN is not activated when the device is executing out ofinternal Program Memory. ALE/PROG (Pin 30).(Not used for AT89S52) • Address Latch Enable. When connecting an 8031 to external memory, Port 0 provides both Address and Data. It is connected to G Pin (Pin 11, Latch Enable)of 74LS373 chip (D Latch). • Not used for ATMEL 89S52. EA/VPP (Programming Voltage, Pin 31). • EA: External Access . • When EA is held high (+5V) the CPU executes out of internal Program Memory. • Holding EA low (0V) forces the CPU to execute out of external memory. In the 80C31, EA must be externally wired low. • In the EPROM devices, this pin also receives the programming supply voltage (VPP) during EPROM programming. • For AT89S52, it will be connected to Vcc.

  17. Alternate Function of Port 3 Pins • P3.0 Receive Data for serial port communication. • P3.1 Transmit Data for serial port communication. • P3.2 Receive External Interrupt 0. • P3.3 Receive External Interrupt 1. • P3.4 Timer 0 Interrupt (Internal) • P3.5 Timer 1 Interrupt (Internal) • P3.6 WR (Bar) Signals of external memory connected in case of 8031. • P3.7 RD (Bar) Signals of external memory connected in case of 8031. • 8051 Interrupts (Five). • 2 external interrupts, • 2 timer interrupts, and • 1 serial interrupt.

  18. SPECIAL FUNCTION REGISTERS OF 8051 • SP: Stack Pointer; DPL: Data Pointer Lower Byte; DPH: Data Pointer Higher Byte; • TCON: Timer Control; TMOD: Timer Mode; • TL0: Timer 0, Low Byte; TH0: Timer 0, Higher Byte • TL1: Timer 1, Low Byte; TH1: Timer 1, Higher Byte • SCON: Serial Communication; SBUF: Serial Buffer; • IE: Interrupt Enable • IP: Instruction Pointer • PSW: Program Status Word • ACC: Accumulator • B: Used by MUL AB and DIV AB • P0: Port 0 internal buffer • P1: Port 1 internal buffer • P2: Port 2 internal buffer • P3: Port 3 internal buffer

  19. EXAMPLE: ER Real Time and Embedded Operating System (RTES or ER) • Writing Real Time and Embedded Operating System for 8051 Microcontroller. • Write a simple operating system for 8051 microcontroller which is required to monitor and control water level in a tank. If the water level falls below a critical level, it should start the water pump automatically. If the level rises above the top level, it should stop the motor. • Guidelines. • There would be two sensors. One for sensing lowest level and the other for sensing highest level. • The sensors would be connected to two pins of a port. These pins/port would be configured as input port. • These sensor pins would be checked in a loop for their status. • When the water level falls below the lowest level, another port pin, configured as output pin, would be set to 1 (Say P2.1). This pin would be connected to an electric relay. If both the sensors are off, give instruction SetB P2.1. which would start the water pump. • When the water level increases above upper level, the pump is stopped by another instruction: ClrP2.1

  20. EXAMPLE: ER Real Time and Embedded Operating System (RTES or ER) • Writing Real Time and Embedded Operating System for 8051 Microcontroller…

  21. EXAMPLE: ER Real Time and Embedded Operating System (RTES or ER) • Writing Real Time and Embedded Operating System for 8051 Microcontroller… ORG 00 ; Configure P1.1 and P1.2 as input pins SetB P1.1 SetB P1.2 ; Now they have high voltage. When water crosses these levels, ; the Sensors should send low voltage (0V) on these pins. ; Configure P2.1 as output pin Clr P2.1 ; Relay should be wired such that ; it also stops the motor Mainloop: ; Check Low level CheckLowLevel:

  22. EXAMPLE: ER Real Time and Embedded Operating System (RTES or ER) • Writing Real Time and Embedded Operating System for 8051 Microcontroller… Mainloop: ; Check Low level CheckLowLevel: JNB P1.1, CheckHighLevel ; P1.1 = 0, Water is above empty level SetB P2.1 ; Tank is Empty , Start Water Pump SJMP Checkgain; Bypass High level checks. ; Let the pump keep running. CheckHighLevel: ; If water is above low level, check upper level JB P1.2, Checkgain ; Water is below Top level Clr P2.1 ; Tank is Full, Stop Water Pump Checkagain: SJmpMainloop END

  23. EXAMPLE: ER Real Time and Embedded Operating System (RTES or ER) • Write an interrupt driven operating system to monitor and control water level in a tank. Water level sensors would be wired on external interrupt pins (P3.2 and P3.3).

  24. EXAMPLE: ER Real Time and Embedded Operating System (RTES or ER) • Write an interrupt driven operating system to monitor and control water level in a tank. Water level sensors would be wired on external interrupt pins (P3.2 and P3.3). Use low level sensor on P3.2 (INT0) and High Level Sensor at Pin P3.3 (INT1). Configure your OS for interrupt handling and write ISRs for the same.

  25. VECTOR ADDRESS OF INTERRUPTS IN 8051

  26. STRUCTURE OF REAL TIME AND EMBEDDED OPERATING SYSTEMS • Steps in executing interrupts in the case of 8051 Series of Microcontrollers:- • Upon activation of an interrupt , the microcontroller finishes the instruction it is executing and saves the address of the next instruction (Program Counter (PC)) on the stack. • It also saves the current status of all the interrupts internally (ie not on the stack). • It jumps to a fixed location in memory in accordance with the Interrupt Vector Table. • If the ISR is only one or two instructions, these may be written there itself. • Generally, the ISR has many instructions. In such cases, a jump instruction is placed at interrupt vector address. • The last instruction in the ISR is RETI (Return from Interrupt). • Upon executing RETI instruction, the microcontroller returns to the place where it was interrupted. First it gets the Program Counter address from the stack by popping the top two bytes of the stack into the PC. Then it starts to execute from that address.

  27. STRUCTURE OF REAL TIME AND EMBEDDED OPERATING SYSTEMS • Interrupts in 8051. There are Six interrupts in 8051. • Reset. When the reset pin is activated, the 8051 jumps to address location 0000. This is the power-up reset. Program execution starts from address 0000. • Timer Interrupts (Two). Two interrupts are set aside for the timers, one for Timer 0 and the other for Timer 1. Memory locations 000BH and 001BH in the interrupt vector table belong to Timer 0 and Timer 1 respectively. • External Hardware Interrupts (Two). Pin No 12 (P3.2) and 13 (P3.3) in Port 3 are for the external hardware interrupts. INT0 and INT1, respectively. These external interrupts are also referred to as EX1 and EX2. Memory locations 0003H and 0013H in the interrupt vector table are assigned to INT0 and INT1 , respectively • Serial Communication Interrupt. Serial communication has a single interrupt that belongs to both receive and transfer. The interrupt vector table location 0023H belongs to this interrupt.

  28. STRUCTURE OF REAL TIME AND EMBEDDED OPERATING SYSTEMS • RESET 0000H to 0002H = 3 Bytes • INT 0: 0003H to 000AH = 8 Bytes • Timer 0: 000BH to 0012H = 8 Bytes • INT 1: 0013H to 001AH = 8 Bytes • Timer 1: 001BH to 0022H = 8 Bytes • Serial COM: 0023H to 002AH = 8 Bytes

  29. INTERRUPT HANDLING IN 8051 ORG 0000H LJMP MainLoop ; Long JMP is a three byte instruction with 16 Bit address ; ISR for Timer 0 to generate square wave ORG 000BH ; This ISR is very small, It is written within 8 Bytes RepeatThis: CPL P2.1 SJMP RepeatThis RETI ; Use RETI to return from ISR ; ISR for External Hardware Interrupt INT 1 ORG 0013H LJMP StartAlarm ; If the ISR is longer than 8 Bytes, jump to subroutine RETI ORG 0030H ; After vector table space MainLoop: ; Keep waiting for interrupts in this loop SJMP MainLoop ; Short JMP is a two byte instruction with Relative Address StartAlarm: SetB P1.0 ; Alarm circuit connected to P1.0 … … ; Write more instructions here RETI ; Use RETI to return from ISR END

  30. INSTRUCTION SET

  31. INSTRUCTION SET

  32. INSTRUCTION SET

  33. INSTRUCTION SET

  34. INSTRUCTION SET

  35. EXTERNAL INTERRUPTS HANDLING IN 8051 • Let us understand the concept of interrupts, how interrupts work, vector address, interrupt priority and how to write an ISR (interrupt service routine). • “Interruption” in English language means a deviation from the normal routine. • We know the processor is always busy executing some kind of instructions. • What if there  occurs an urgent condition that we need to pause the processor from its current activities for some time and make it execute/do something else? • Also we need to resume the processor back to its operations after executing our “urgent condition”. • To meet such a demand, 8051 micro controller has got a system called “Interrupts”.

  36. EXTERNAL INTERRUPTS HANDLING IN 8051 • An interrupt is usually a signal from the external world or a command from the internal program (called software interrupt), which forces the processor to pause its current activities and then jump to another location to execute another set of predefined activities. • While doing so the processor will save its currents status and location to a temporary storage area (to resume the current activities after finishing the interrupt). • The process of jumping to another location, after receiving the interrupt signal is known as “servicing the interrupt”.

  37. EXTERNAL INTERRUPTS HANDLING IN 8051 Interrupt sources • In an 8051 micro controller there are • 2 external interrupts, • 2 timer interrupts, and • 1 serial interrupt. • External interrupts are – external interrupt 0(INT0) and external interrupt 1 (INT1). • Timer interrupts are Timer 0 interrupt and Timer 1 interrupt. • A serial interrupt is given for serial communication with the micro controller (transmit and receive) . • All these four interrupts, when evoked serve or execute a particular set of predefined activities known as “Interrupt Service Routines”. • It’s way of functioning is similar to the “subroutines” we write while developing a complete program. • In the case of 8051, the interrupt service routines(ISR) of each interrupt must begin from a corresponding address in the program memory. • This address from which an ISR begins is called the vector address of the interrupt.

  38. EXTERNAL INTERRUPTS HANDLING IN 8051

  39. EXTERNAL INTERRUPTS HANDLING IN 8051 Interrupt Priority • All the 5 interrupts of 8051 have got different priorities. • Interrupts are serviced according to it’s priority order. • From the table above, you can see that INT0 has the highest priority of 1 and Timer 0 comes next with priority value 2. • The order of priority works like this – consider a case where two interrupts are raised at the same time – one from INT0 and another from Timer 1 interrupt. Now which one would be served first? • In such a case, processor would serve the interrupt according to it’s priority. • In our case INT0 is of high priority (priority order 1)and Timer 1 interrupt is of low priority (priority order 4). So processor will execute ISR of INTO first and then later, after finishing ISR of INT0, processor will begin executing ISR of Timer 1 interrupt.

  40. EXTERNAL INTERRUPTS HANDLING IN 8051 Interrupt Priority… • From the figure above, you may note that INTO is an alternate function P3.2 and INT1 is an alternate function of P3.3. • A signal received at these pins will evoke the interrupts accordingly. But not all signals will evoke the interrupt! • The signal received at pins should be either a low level one or it should be a falling edge signal to evoke the corresponding interrupt. • However, to serve the interrupt upon receiving the signal at pins, the man who programs 8051 should preprocess a few bits of three SFRs namely TCON, IE and IP. • Let’s examine them. 

  41. 8051 TIMER CONTROL (TCON) SPECIAL FUNCTION REGISTER http://www.circuitstoday.com/external-interrupts-handling-in-8051

  42. 8051 TIMER CONTROL (TCON) SPECIAL FUNCTION REGISTER • TCON is a bit addressable SFR. • Out of the 8 bits, only the lower 4 bits are concerned with external interrupts. • The upper 4 bits deals with interrupts from Timers. • The lower four bits are TCON.0 (IT0), TCON.1 (IE0), TCON.2 (IT1) and TCON.3 (IE1). • You can refer the figure given above for a better understanding. • Out of these 4 bits, bits 0 and 1 – that means – TCON.0 and TCON.1 are concerned with external interrupt 0 (INT0), where as bits 2 and 3 – TCON.2 and TCON.3 are concerned with external interrupt 1 (INT1). • Out of these bits only TCON.0 and TCON.2 are directly manipulated by the programmer while dealing with an external interrupt. • Bits TCON.1 (IE0) and TCON.3 (IE1) are manipulated by the processor itself. 

  43. 8051 TIMER CONTROL (TCON) SPECIAL FUNCTION REGISTER • Bits TCON.1 (IE0) and TCON.3 (IE1) are manipulated by the processor itself.  • An external signal received at INTO would set the bit TCON.1 (also known as IE0) and will be cleared by the processor itself, after it branches to the corresponding ISR located at 0003H. • Similarly TCON.3 is set when an interrupt signal is received at INT1 and would be cleared by processor after branching.  • The other 2 bits TCON.0 and TCON.2 are used for selecting “type of signal” received. • TCON.0 (or IT0) is set to 0 – if the interrupt at INT0 is to be evoked by a low level signal. • If TCON.0 is set to high, then the interrupt at INT0 would be evoked by a falling edge signal (high to low transition). • Same is the case with TCON.1 – if set to 0 then low level signal would raise an interrupt at INT1 and if set to high, then a falling edge signal would do the job.

  44. 8051 TIMER CONTROL (TCON) SPECIAL FUNCTION REGISTER

  45. http://www.circuitstoday.com/external-interrupts-handling-in-8051http://www.circuitstoday.com/external-interrupts-handling-in-8051

  46. 8051 ITERRUPT ENABLE (IE) SPECIAL FUNCTION REGISTER • There are 3 bits associated with external interrupts in IE – they are bits 0, 2 and 7. • The main purpose of this SFR is to enable/disable different interrupts based on whether it’s corresponding bits are set or not. Refer the figure above. • IE.7 – is known as global interrupt bit – which when set to ’0′ – disables all kinds of interrupts in 8051. • Only if this bit is set to ’1″, any kind of interrupt would be enabled in 8051. • If this bit is set to 1, programmer can then individually enable or disable all other interrupts INT0, INT1, Timer interrupts (0 and 1) and serial interrupt. • IE.0 – If set to ’1′ – it enables INT0 and if set to ’0′ – INT0 would be disabled. So in order to enable external interrupt 0 (INT0) – IE.7 and IE.0 should be set to ’1′. • IE.2 – Similar to IE.0 – IE.1 enables/disables external interrupt 1 (INT1).

  47. 8051 ITERRUPT ENABLE (IE) SPECIAL FUNCTION REGISTER • There are 3 bits associated with external interrupts in IE – they are bits 0, 2 and 7. • The main purpose of this SFR is to enable/disable different interrupts based on whether it’s corresponding bits are set or not. Refer the figure above. • IE.7 – is known as global interrupt bit – which when set to ’0′ – disables all kinds of interrupts in 8051. • Only if this bit is set to ’1″, any kind of interrupt would be enabled in 8051. • If this bit is set to 1, programmer can then individually enable or disable all other interrupts INT0, INT1, Timer interrupts (0 and 1) and serial interrupt. • IE.0 – If set to ’1′ – it enables INT0 and if set to ’0′ – INT0 would be disabled. So in order to enable external interrupt 0 (INT0) – IE.7 and IE.0 should be set to ’1′. • IE.2 – Similar to IE.0 – IE.1 enables/disables external interrupt 1 (INT1).

  48. 8051 ITERRUPT PRIORITY (IP) SPECIAL FUNCTION REGISTER

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