Lecture 5: MIPS R2000 Instructions and the Intel x86 Architecture

Nov 08, 2012

350 likes | 637 Views

Administration. Chapter 3 homework will be posted by next class (5 Feb). Due following Tuesday (10 Feb)Course is online on Blackboard. Today's Objectives. Complete review of MIPS ISAContrast MIPS to the Intel x86 Architecture. . . . Multiply / Divide. Perform multiply, divide mult

Share Presentation

Embed Code

Link

geraldine

Download Presentation

Lecture 5: MIPS R2000 Instructions and the Intel x86 Architecture

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

CS325 Instructions: Language of the Machine MIPS ARCHITECTURE - AN INTRODUCTION TO THE INSTRUCTION SET by N. Guydosh 2/2

CS325 Instructions: Language of the Machine MIPS ARCHITECTURE - AN INTRODUCTION TO THE INSTRUCTION SET by N. Guydosh 2/2/04+. MIPS Approach.

607 views • 35 slides

MIPS Assembly Language

MIPS Assembly Language. CPSC 321 Computer Architecture Andreas Klappenecker . MIPS Assembly Instructions. add $t0, $t1, $t2 # $t0=$t1+$t2 sub $t0, $t1, $t2 # $t0=$t1-$t2 lw $t1, a_addr # $t1=Mem[a_addr] sw $s1, a_addr # Mem[a_addr]=$t1. Assembler directives.

985 views • 30 slides

MIPS mul div, and MIPS floating point instructions

MIPS mul div, and MIPS floating point instructions. SPIM. Run codes with SPIM. Use any editor to write the source file. Run PCSpim, load the source file. F10 to step through the code. Complete MIPS code. It has a data segment and a code (text) segment.

986 views • 13 slides

Lecture 3: MIPS Instruction Set

Lecture 3: MIPS Instruction Set. Today’s topic: More MIPS instructions Procedure call/return Reminder: Assignment 1 is on the class web-page (due 9/7). Memory Operands. Values must be fetched from memory before (add and sub) instructions can operate on them Load word

524 views • 24 slides

CpE 442 Computer Architecture and Engineering MIPS Instruction Set Architecture

CpE 442 Computer Architecture and Engineering MIPS Instruction Set Architecture. Overview of Today’s Lecture: MIPS et al. Review from Last Lecture (3 minutes) MIPS ISA (20 minutes) More MIPS (25 minutes) MIPS (VAX, 80x86?) (25 minutes). Review: Instruction Set Design. software.

700 views • 28 slides

MIPS Assembly Language I

MIPS Assembly Language I. Computer Architecture CPSC 321 Andreas Klappenecker. MIPS. The MIPS assembly language has arithmetic instructions (add, sub,…) logical instructions (and, or,…) branch instructions (bgtz, bne, …) jump instructions (j, jr, …)

545 views • 28 slides

Lecture 5. MIPS Processor Design Pipelined MIPS #1

COMP212 Computer Architecture. Lecture 5. MIPS Processor Design Pipelined MIPS #1. Prof. Taeweon Suh Computer Science Education Korea University. Processor Performance. Performance of single-cycle processor is limited by the long critical path delay

520 views • 27 slides

Lecture 5. MIPS Processor Design Pipelined MIPS #2

COMP212 Computer Architecture. Lecture 5. MIPS Processor Design Pipelined MIPS #2. Prof. Taeweon Suh Computer Science Education Korea University. Pipelined Datapath. Pipelining Example . add $14, $5, $6. lw $13, 24($1). add $12, $3, $4. sub $11, $2, $3. lw $10, 20($1). 0. M. u. x.

887 views • 61 slides

CEG3420 Computer Design Lecture 4 MIPS Instruction Set

CEG3420 Computer Design Lecture 4 MIPS Instruction Set. Philip Leong. Instructions:. Language of the Machine More primitive than higher level languages e.g., no sophisticated control flow Very restrictive e.g., MIPS Arithmetic Instructions

717 views • 43 slides

COMS 361 Computer Organization

COMS 361 Computer Organization. Title: Instructions Date: 9/30/2004 Lecture Number: 11. Announcements. Homework 4 Due 10/05/04. Review. SPIM MIPS simulator SPIM program (exit.s) Comments Assembler directives .text .data Labels Instructions Data MIPS DataPath

235 views • 13 slides

MIPS Processor

MIPS Processor. Chapter 12 S. Dandamudi. Introduction Evolution of CISC Processors RISC Design Principles MIPS Architecture. Outline. Introduction. CISC Complex instruction set Pentium is the most popular example RISC Simple instructions Reduced complexity

465 views • 16 slides

COE 1502 MIPS Multicycle CPU Architecture Sequential Logic & Control

COE 1502 MIPS Multicycle CPU Architecture Sequential Logic & Control. MIPS Instruction Set Architecture. Instruction Set Architecture Interface between programmer/user and hardware Instruction set Instruction encoding/representation 6800-series and MIPS are two different ISAs

508 views • 32 slides

MIPS mul div, and MIPS floating point instructions

MIPS mul div, and MIPS floating point instructions. Multiply and Division Instructions. mul rd, rs, rt puts the result of rs times rt in rd div rd, rs, rt A pseudo instruction puts the quotient of rs/rt into rd. hi and lo. Special ‘addressable’ registers

520 views • 17 slides

Intel SIMD architecture

Intel SIMD architecture. Computer Organization and Assembly Languages Yung-Yu Chuang 2008/1/5. Overview. SIMD MMX architectures MMX instructions examples SSE/SSE2

1.01k views • 80 slides

Dan Garcia

CS 61C: Great Ideas in Computer Architecture MIPS Instruction Representation II. Dan Garcia. Review of Last Lecture. Simplifying MIPS: Define instructions to be same size as data word (one word) so that they can use the same memory

700 views • 51 slides

Advanced Computer Architecture 5MD00 / 5Z033 MIPS Instruction-Set Architecture

Advanced Computer Architecture 5MD00 / 5Z033 MIPS Instruction-Set Architecture. Henk Corporaal www.ics.ele.tue.nl/~heco/courses/aca TUEindhoven 2011. Topics. Instructions & MIPS instruction set Where are the operands ? Machine language Assembler Translating C statements into Assembler

640 views • 32 slides

Lecture 05: INSTRUCTION REPRESENTATION

Lecture 05: INSTRUCTION REPRESENTATION. Overview – Instruction Representation. Big idea: stored program Instructions as numbers Instruction encoding MIPS instruction format for Add instructions MIPS instruction format for Immediate, Data transfer instructions.

395 views • 23 slides

Lecture 8. MIPS Instructions #2 – Memory Access (Load/Store) Instructions

2010 R&E Computer System Education & Research. Lecture 8. MIPS Instructions #2 – Memory Access (Load/Store) Instructions. Prof. Taeweon Suh Computer Science Education Korea University. Why Should CPU Access Memory?. Memory (DDR).

791 views • 22 slides

Chapter 3: Instructions

Chapter 3: Instructions. CS 447 Jason D. Bakos. Assembly Language Instructions. We’re going to use the MIPS R2000 instruction set for the projects in this course Review: Assembly language instructions are English words that represent binary machine language instructions.

674 views • 41 slides

CS152 Computer Architecture and Engineering Lecture 2 Review of MIPS ISA and Performance

CS152 Computer Architecture and Engineering Lecture 2 Review of MIPS ISA and Performance. Overview of Today’s Lecture. ISA, Addressing, Format (20 min) Administrative Matters (5 min) Operations, Branching, Calling conventions (25 min) Break (5 min) MIPS Details, Performance (25 min).

713 views • 51 slides

Microprocessors

Microprocessors. The MIPS Architecture (User Level Instruction Set) Mar 21st, 2002. Generations of MIPS. Original architecture R2000 Later version R3000-R10000 Added instructions Moved from 32-bit to 64-bit Doubled number of fpt registers Removed some restrictions

440 views • 33 slides

Intel Architecture

Intel Architecture. Changes in architecture. Software architecture: Front end (Feature changes such as adding more graphics, changing the background colors, and improving the overall look and feel) Back end (Rearranging data, unrolling loops, and/or using new instructions)

540 views • 28 slides

More Related

Lecture 5: MIPS R2000 Instructions and the Intel x86 Architecture

Lecture 5: MIPS R2000 Instructions and the Intel x86 Architecture

Presentation Transcript

CS325 Instructions: Language of the Machine MIPS ARCHITECTURE - AN INTRODUCTION TO THE INSTRUCTION SET by N. Guydosh 2/2

MIPS Assembly Language

MIPS mul div, and MIPS floating point instructions

Lecture 3: MIPS Instruction Set

CpE 442 Computer Architecture and Engineering MIPS Instruction Set Architecture

MIPS Assembly Language I

Lecture 5. MIPS Processor Design Pipelined MIPS #1

Lecture 5. MIPS Processor Design Pipelined MIPS #2

CEG3420 Computer Design Lecture 4 MIPS Instruction Set

COMS 361 Computer Organization

MIPS Processor

COE 1502 MIPS Multicycle CPU Architecture Sequential Logic &amp; Control

MIPS mul div, and MIPS floating point instructions

Intel SIMD architecture

Dan Garcia

Advanced Computer Architecture 5MD00 / 5Z033 MIPS Instruction-Set Architecture

Lecture 05: INSTRUCTION REPRESENTATION

Lecture 8. MIPS Instructions #2 – Memory Access (Load/Store) Instructions

Chapter 3: Instructions

CS152 Computer Architecture and Engineering Lecture 2 Review of MIPS ISA and Performance

Microprocessors

Intel Architecture

COE 1502 MIPS Multicycle CPU Architecture Sequential Logic & Control