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hayles@ni.com

Integrating Timing and Free-Running Actors with Dataflow Tim Hayles Principal Engineer National Instruments September 9, 2008. hayles@ni.com. Agenda. What is LabVIEW Dataflow? Why is timing important to NI? Further motivation for this research Key elements Asynchronous Data Wires

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hayles@ni.com

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  1. Integrating Timing and Free-Running Actors with DataflowTim HaylesPrincipal EngineerNational InstrumentsSeptember 9, 2008 hayles@ni.com

  2. Agenda • What is LabVIEW Dataflow? • Why is timing important to NI? • Further motivation for this research • Key elements • Asynchronous Data Wires • Asynchronous Timing Wires • A small set of “Free Running” Actors • Implementation Details • Examples

  3. What is LabVIEW Dataflow? • aka Structured Dataflow • Loops, cases, sequences, … • aka Homogenous Dataflow • Always a single token on a wire • aka simply as ‘G’ • Dynamically scheduled • Data driven • Simple to use and understand • Widely successful

  4. LabVIEW Dataflow

  5. Why is Timing Important to NI? • We make I/O products • I/O timing requires • Configuration • Routing • Synchronization • Multiple subsystems on one board • Multiple boards in one chassis • Multiple chassis • I/O timing must play well with application timing

  6. DAQmx STC Clock Model

  7. DAQmx API

  8. Dialog Configuration

  9. Maybe this would work …

  10. Data Acquisition: Dataflow API • Generate a single, re-triggerable pulse, delayed from the trigger • DAQmx dataflow configures a circuit and activates it • Clearing the task has the side effect of disabling the circuit

  11. Data Acquisition to the Pin • This mixed model is much closer to the actual hardware • Opening up the pulse generator can reveal more detail

  12. Now we also want … • To further exploit parallelism even between nodes sharing a data transformation • To incorporate common data exchange techniques into the language • First class support for • Pipelines • Multi-rate • Streaming • Timing • Offer a multi-target programming canvas • Deployment, startup and shutdown order

  13. Asynchronous Wire • No inherent semantics • All behavior conferred by implementation outside LabVIEW – though written in LabVIEW • One wire for data • One wire for timing • Producer and consumer nodes become “free-running” actors firing based on • Data or space availability • Timing

  14. Timing Wires • Carry not time stamps, but ‘ticks’ • Time stamps are data • Ticks are unit-less and ephemeral state changes • Voltage transition • Boolean transition • Route signals • Clock domains for FPGA logic • Clocks for I/O timing and triggering • Triggers for timing computations • Abstract • Copper traces (actual wires) • Memory locations (‘soft’ clocks and triggers)

  15. Timing Wires

  16. Timing Wires • Triggers can be polymorphic to accept time stamps (but that’s a data wire)

  17. Asynchronous Data Wire • Buffered • Writer usually, though not always, ‘owns’ the buffer • Besides depth, buffer has type • Register • Fifo • Circular buffer • Type determines behavior • aka data exchange policy

  18. IF-RIO Experiment • RF Transceiver product • Async wires and actors used on same canvas as LabVIEW dataflow

  19. IF-RIO Experiment Now • A new palette of seven async actors and two dataflow actors • FPGA only

  20. IF-RIO Experiment – FPGA code

  21. Harnessed User G Code • False case writes false to Start DAC otherwise empty • No notion of buffering policies used in async layer

  22. IF-RIO Experiment – FPGA code

  23. Harnessed User G Code • LabVIEW dataflow makes the copy of the data • When the first copy is made, Start goes true and the DAC begins consuming data

  24. Harness Integration of Dataflow • A technique for complete separation of the MOCs • The VI is pure LabVIEW dataflow • The free-running Harness generates the code to read and write the asynchronous wires and call the VI • Code generation is optimized for streaming

  25. Harness Generated Code • If the harnessed VI does not support any of the streaming protocol terminals, the IP Block only executes when • There is no pending write • A read was succesful

  26. System Diagram • MOC integration • Complete separation • Limited mixing • I/O integration • Discover • Configure • Operate • Target integration • Multiple targets • One canvas

  27. Four Target System Diagram

  28. G behind System Diagram • Just the accessors and terminals here

  29. G behind System Diagram G code must provide the loop

  30. Three Target System Diagram

  31. Physically Constrained View

  32. More System Diagram Research • Relation to timestamp based MOCs • MOC hosting • Debugging • Simulation • Scheduling • A state machine for deployment, etc • Communication between the state machine and the hosted code • Mapping IP among processing resources

  33. Contact Information • hayles@ni.com • www.ni.com\labview • Local contact: hugo.andrade@ni.com

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