Multi-Phase, Stackable Controllers For Non- Portable Application Nancy Zhang

1. Multi-Phase, Stackable Controllers For Non- Portable Application Nancy Zhang Applications Engineer Computing Power Management

2. Agenda • Introduction • TPS40140 Dual Phase Stackable Controller • TPS40180 Single Phase Stackable Features • New 4-phase TPS40140EVM Performance • Conclusions

3. Traditional Multiphase Buck Controller Advantages: • Exactly match the phase numbers required by applications Disadvantages: • Hard to re-use the design for different applications • No flexibility to expand the system for higher current requirement • Hard to layout for increased phase numbers

4. Stackable Buck Controller Solution Flexibility!! Advantages: • Very flexible for system expansion • Can easily stack with the same converter to achieve higher power • Identical stackable design block reducing layout complexity • Interleaved phases reduces input ripple for multiphase and multi-output applications • Very good for universal power solution design • Dynamic Phase Management • Single part number easy for part number and production control Disadvantages: • None

5. Universal Stackable Building Blocks Build ANY size Power supply with just 2 parts !!!! TOOL BOX Tps40180 Single phase Block Single Phase Tps40180 Tps40140 Two phase Block Two Phase Tps40140 Tps40140 Dual Output Block Dual Output

6. Multiphase - Single Output Vo Vin Single phase application (up to 25A) Vin Vo Tps40180 Single phase Block Tps40180 Single phase Block Vin Tps40140 Two phase Block Vo COMP CLKIO or Tps40180 Single phase Block

7. Multiphase - Single Output Vo Vo Three phase output application (up to 75A) Vin Tps40180 Single phase Block Tps40140 Two phase Block Four phase output application (up to 100A) Vin Tps40140 Two phase Block Tps40140 Two phase Block

8. Multiple Output Rails Three Output Rails with Synchronization Tps40180 Single phase Block Vo1 Vin Vo1 Vin Tps40180 Single phase Block Tps40180 Single phase Block Vo2 or Vo2 Tps40140 Dual Output Block Vo3 Tps40180 Single phase Block Vo3

9. TPS40140 Dual-Phase Stackable Controller Features Benefits • 1V to 40V Input Voltage Range • Internal 5V regulator • 0.7V to 5.8V Output Voltage Range • Dual-phase Interleaved up to 16 phases • Programmable switching frequency up to 1MHz • 0.5% 0.7V reference voltage • Current mode control with forced current sharing • Support pre-biased outputs • Power sharing from different input voltage rail • True remote sense differential amplifier • Programmable input under voltage lockout • Resistive or Inductor DCR current sensing • PGOOD, OCP, OVP, UVP • 36pin QFN Thermally Enhanced Package • Supports multi bus rails • No need for external 5Vbias • Easy-to-use solution for voltage rails up to 40A • Reduced Input, Output Ripple, Save input, output caps • Optimized Efficiency and high power density • Tight Output Voltage Accuracy • Supports all MLCC Designs • No output glitch when loads are pre-charged • Optimized input current from input rail • Improve regulation and ease layout constrains • Flexibility design • Complete Control, power sequencing and system protection • High Power Density, Excellent Thermal Performance Applications • Servers, Notebook/Netbook Computers • Networking Equipment • Telecommunications Equipment • Graphic Cards and Internet Serves • Low-voltage, Point-Of-Load Converters • DC Power Distributed System 9

10. TPS40140 Key Features Stackable!!! • Selectable Dual-Output or 2-Phase • Interleaved Operation, Stackable up to 16 Phases • VDD From 4.5 V to 15 V, With Internal 5V Regulator • VOUT From 0.7 V to 5.8 V • True Remote Sensing Differential Amplifier • Programmable Switching Frequency Up to 1MHz/Phase • Soft Start without/with Pre-biased Output • Resistive Divider Sets Input Under voltage Lockout • Resistive or Inductors DCR Current Sensing • Peak Current Mode Control with Forced Current Sharing

11. Functional Diagram Phase1 Driver Current Loop1 Voltage Loop1 COMPx Voltage Loop2 Current Loop2 Phase2 Driver UVLOx Enable PHSEL CLKIO

12. Stackable Configurations • TPS40140 can be stackable up to 16 phases with synchronization • One TPS40140 is configured as master and the other chips are configured as slave • Three wire connections are required: CLKIO, COMP, PHSEL • CLKIO synchronize all the chips • COMP force the current balance • PHSEL provides the right phase information

13. Digital Synchronization Scheme PHSEL Pin: • There are two CLK schemes in the design, • The 6-Phase CLK scheme is to achieve symmetric phase balance for a 6-phase or 12-phase converter • The 8-Phase CLK scheme is to achieve symmetric phase balance for 2,4,8,16 phase converter

14. Digital Synchronization Scheme PHSEL Pin:

15. For example: 4-phase Configuration PHSEL Pin: • One phase resistor is connected to the PHSEL pin. • COMP and CLKIO pins are connected together • R=39.2k R

16. For example: 3-phase + Single Channel Configuration PHSEL Pin: • M_Ch1, M_Ch2 and S_Ch1 construct the 3-phase converter, S_Ch2 is the single channel output • The master chip is not only voltage loop master, also the CLK master

17. Master/ Slave Operation CLKIO Pin: • Only three pins connection are required • CLKIO, PHSEL, • COMP (if current sharing) • Required a 10k resistor connected • from CLKIO to GND • at Master- Slave operation • When the master device is shut down or power off, the master CLKIO • Pin goes to a high impedance state and there is no other active discharge part. • The slave controllers looks at the CLKIO line to determine if the system is • supposed to be running or not. A level below 0.5V on CLKIO is required. • This 10k resistor will ensure the CLKIO line falls to GND quickly

18. How to Disable Slave Modules? • Case 1: Parallel module without CLK distribution UVLO_CEx Pin • This application is mainly for module makers to do current sharing between modules with a single pin • The Pin is COMP for TPS40140 application • One Module is set to master and the other modules are set to slave • The slave modules can be disabled by toggle the UVLO_CEx pin to GND.

19. How to Disable Slave Modules? • Case 2: for stackable applications with distributed CLK • To disable a slave module, the UVLO pin might not be directly pulled to GND that will also pull down the CLK VREG is turned off when Both UVLO pins are shorted to GND, then the CLK signal at CLKIO pin is also clamped to GND by D1.

20. How to Disable Slave Modules? • Case 2: for stackable applications with distributed CLK • Method1: Short one UVLO pin to GND while the other UVLO pin is still higher than 1.5V • This will shut down one channel and the other channel is still running or in standby mode(1.5V<UVLO<2V) • Method2: Held UVLO pin to be less than 2V and higher than 1.5V, so the chip is in standby mode • Method3: Ground the PHSEL pin of the master that will shut off all the slave modules, but the master is still running

21. How to Disable Slave Modules? • Case 2: for stackable applications with distributed CLK • Method 4: Use a jumper to disconnect the CLK to the slave module

22. How to Disable Slave Modules? • Case 2: for stackable applications with distributed CLK • Method 5: Turn off all the modules including the master by disconnect the PHSEL resistor string When SW2 is open, the PHSEL Pin at the master will rise to be over 4V and stop the master controller, hence the slave modules are also ceased.

23. VOUT and GSNS Pin The unity gain differential amplifier has a high bandwidth to achieve improved regulation at user defined point of load and eases layout constrains. The output voltage is sensed between the VOUT and GSNS pins. The output voltage programming divider is connected to the output of the amplifier, the DIFFO pin. Output 0.7V to 5.8V Voltage Range You can bypass differential amplifier. Just short VSNS,GSNS to GND and leave DIFFO open Remote Sense

24. Output Voltage Setting DIFFO Pin • Two resistors, R1 and RBIAS sets the output voltage Or DIFFO

25. Programmable Switching Frequency • RT pin • Master: • Frequency Setting by Rt • Can synchronize to external clock • Slave: • RT pin tied to BP5 • Where • fPH is the phase switching frequency in kHz • Rt is in kΩ • There are two clock scheme in the chip called 8-phase and 6-phase scheme. • This equation gives the resistor selection for a 8-phase scheme. For a 6-phase scheme, the switching frequency is 4/3 times higher

26. Start Up and Shut Down Sequence It shows a typical start up with the VDD applied to the controller and then the UVLO-CEx being enabled. Shut down occurs when the VDD is removed.

27. Soft Start without Pre-biased Output • TRKx Pin • Master: • When UVLO_CEx is high and POR is cleared, the external soft start capacitor is charged • with 12-μA. • The rising voltage across the capacitor serves as a reference for the error amplifier • When TRK pin reaches the level of the reference voltage 0.7V, the converter’s output • reaches the regulation point • When TRK pin voltage reaches 1.4 V, the PGOOD pin goes high at this time. • Slave: • Tie TRKx pin to BP5 for track function Css: Soft start capacitor in Farads Css connected from TRKx to GND Tss: Soft start time in seconds

28. Soft Start with Pre-biased Output • TRKx Pin (Master): • When UVLO_CEx is high and POR is cleared, the external soft start capacitor is charged with 6-μA until the TRK pin voltage is equal to the FB voltage • When the first PWM pulse occurs, the charging current is increased to 12-μA. The rising voltage across the capacitor serves as a reference for the error amplifier • When TRK pin voltage reaches the level of the reference voltage 0.7V, the converter’s output reaches the regulation point • When TRK pin voltage reaches 1.4 V, the PGOOD pin goes high at this time. • TRK pin voltage continues to rise to 2.4V which is clamped internally • If the pre-biased output voltage is greater than the regulation voltage, the controller does not start.

29. Soft Start with Pre-biased Output TRKx Pin:

30. Programmable Under Voltage Lock Out UVLO_CEx Pin • A resistor divider is connected to UVLO_CEx pins • Works as Enable function • The controller begins to work when the voltage on the • UVLO_CEx pins is over 2V. • The internal regulators are enabled when the voltage • on the UVLO_CEx pins exceeds 1.5 V, but switching • commences when the voltage is 2 V. • This pin can be used to disable individual output for • dual channel configuration; for master-slave configuration • UVLO hysteresis is only 40mV (Add three components • to improve hysteresis to 1V or 2V)

31. UVLO Hysteresis Improved Circuit Add R39(39.2k), D5 and C21(47pF) increase hysteresis from 40mV to 2V LDRVx

32. Current Sensing Scheme CSx and CSRTx Pin • TPS40140 uses Inductor DCR or sensing resistor to obtaining current feedback information. DCR sensing is preferred as it is a lossless approach. • If the R1C1 time constant is matched to the L/DCR time constant, the voltage across C1 will be equal to the voltage across DCR. A good starting point is equating C1 = 0.1uF. Then R1 is calculated below.

33. Current Sensing Scheme • CSx and CSRTx Pin • The peak voltage of Vc should not exceed ±60 mV because that is • the maximum differential input voltage of the current sensing amplifier. • If the voltage Vc exceeds ±60 mV, a resistor can be added in • parallel with C1 to provide the voltage attenuation. The ratio

34. Current Sensing Scheme CSx and CSRTx Pin • As mentioned in the previous slide, the maximum differential input voltage of the CS amplifier is +/-60mV • The offset voltage is +/-2mV that will affect the current sharing accuracy • i.e. DCR=1mohm, the sensing current tolerance is 2A • The CS amplifier gain is typically 13

35. Sub-harmonics Consideration Inductor Selection • Sub-harmonics in peak current mode control systems can cause pulse skipping • To avoid sub-harmonics make the inductor current rising slope smaller than 2 x Vramp. • The following equation gives the L/DCR consideration achieve this Where Vin is input voltage, Vramp is the internal ramp voltage of 0.5V, and Ac is the current sensing amplifier gain of 12.5.

36. Current Balance COMPx Pin • A 2-phase single output configuration is used here as an example

37. Current Balance • COMPx Pin • The sensed current is amplified with a ratio of 12.5 and then is subtracted from • COMP. • The subtracted voltage Ve is then compared with the ramp to generate the duty • cycle command. • COMP is the same for the two channels. Also, the two ramps are also the same in • magnitude although with 180 degree phase shift. • So, i.e. 1st channel has current , then Ve1 is decreased, hence the duty • cycle of 1st channel is reduced that will reduce the current in that channel and • then bring back to current balance.

38. Current Balance COMPx Pin 1. 2. Ipeak: inductor peak current Vshr: ramp valley voltage RAMP: it is equal to 0.5V The currents are balanced because they have the same COMP, Vshr and RAMP Then the tolerance of inductor DCR (Rsns) will be the peak current tolerance.

39. Current Balance COMPx Pin • To parallel modules withoutoptimized phase shift, Single pin is required for current balance. • The TRK1 pin in the slave chip should be tied to +5V to disable the error amplifier. • The COMP pins are tied together to force current balancing. • Vshr pins do not have to be connected because Vshr is very accurate between chips. • Its tolerance is afew mVs. • So with the same equation shown above, we can find the paralleled channels are current balanced.

40. Over Current Protection ILIMx and VSHARE Pin (Master): • If the over-current condition persists for seven (7) clock cycles the converter shuts down and initiates a hiccup mode restart. • In hiccup mode, the TRKx pin is periodically charged and discharged. • After seven hiccup cycles, the controller attempts another soft-start cycle to restore normal operation. If the overload condition persists, the controller returns to the hiccup mode. ILIMx Pin(Slave): Tied to GND Over Current Setting By R1, R2 on lLIMx and VSHARE pin

41. Over Current Protection ILIMx and VSHARE Pin: • U7 shows the over current protection. • If COMP voltage is greater than the ILIM • voltage, over current occurs. • VOUT, VSHR and the 20uA current • source from ILIM pin will determine the • ILIM voltage • IPEAK is the peak value of the phase • current

42. Over Current Protection • How to calculate R1 and R2? for 8-phase CLK scheme for 6-phase CLK scheme Ilim voltage is also set by R1 and R2

43. Over Current Protection • How to calculate R1 and R2? We have calculation spreadsheet to help calculate R1, R2 Example: for Vin=12V, with 8-phase CLK scheme: DCR unit in mohm, Ipeak unit in Amp Ipeak is the phase current With 6-phase CLK scheme: R1 and R2 unit in Kohm

44. Fault Protection • Fault Masking Operation • If the TRKx pin voltage is externally limited below the 1.4-V threshold, the controller does not respond to an undervoltage fault and the PGOOD output remains low. • The overcurrent protection continues to terminate PWM cycle every time the threshold is exceeded, but the hiccup mode is not entered.

45. Peak Current Mode Control Loop Compensation Peak Current Mode Control Transfer Function Type II Compensator is employed to compensate the loop COMP Vo or DIFFO

46. TPS40140 Loop Compensation Spreadsheet

47. TPS40140 Component Selection Spreadsheet

48. TPS40180 New features • Single phase operation • Stackable to 8 Phases, multiple controllers can occupy any phase • eTrimTM allow the user to trim the reference voltage in system. Tis will tighten overall output tolerance by trimming out errors caused by resistor divider and other system tolerance. • Thermal warning and thermal shutdown • Most Features are similar to TPS40140 • 24 pin QFN

49. New 4-Phase TPS40140EVM CSD16406Q3 CSD16401Q5

50. New 4-Phase TPS40140EVM Schematic1