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Techniques for Precise Delay Measurement Circuits in Integrated Circuits

Explore methods & factors in circuit design for measuring time differences in ICs with high resolution, like digital counters, ring oscillators, and Vernier delay lines.

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Techniques for Precise Delay Measurement Circuits in Integrated Circuits

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  1. Literature Review – Delay Measurement Techniques Yuta Toriyama yuta@ee.ucla August 20, 2010

  2. Outline Introduction Problem statement Significance of stated problem Techniques Analog Digital Counter Ring Oscillator Vernier Delay Line Summary

  3. Problem Statement Design a circuit that can measure the time difference between the rising edge of one signal to the rising edge of another Factors: Resolution Complexity of circuitry Test time etc…

  4. Significance of Delay Measurement ICs In General: Characterization Increased sensitivity/variation in deep sub-micron technologies Higher clock rates, more signal paths critically timed Yield Increasing difficulty of signal access for external test My case: Characterization of STTRAM Read delay measurement

  5. Charging A Capacitor Create an analog voltage across the capacitor depending on how long the EN pulse is high Requires ADC; all elements of circuit need to be ideal; etc.

  6. Count the number of rising edges of a fast clock Simple to implement Resolution limited by clock frequency Digital Counter

  7. Digital Counter Count the number of rising edges of a fast clock Simple to implement Resolution limited by clock frequency

  8. Ring Oscillator Count the number of rising edges w/ CUT included High Resolution (limited by mux delay) Signal delay being measured must occur multiple times

  9. Vernier Delay Line Two delay lines with slightly different delays in each buffer Detect where in the delay line the edges occur at the same time

  10. Vernier Delay Line (cont.) Very fine resolution Sensitive to supply, layout Variation can cause non-linearity / non-monotonicity!

  11. Summary • Tradeoff • Resolution/Accuracy • Complexity • Test time • STTRAM chip • Digital Counter implemented for read delay measurement • In simulation: ~100ps resolution (Richard)

  12. References Farahat, M.A.; Farag, F.A.; Elsimary, H.A.; , "Only digital technology analog-to-digital converter circuit," Micro-NanoMechatronics and Human Science, 2003 IEEE International Symposium on , vol.1, no., pp. 178- 181 Vol. 1, 27-30 Dec. 2003. Jochen Rivoir; , "Fully-Digital Time-To-Digital Converter for ATE with Autonomous Calibration," Test Conference, 2006. ITC '06. IEEE International , vol., no., pp.1-10, Oct. 2006. Sunter, S., “BIST Techniques for Delay and Jitter inNanometer Technology ICs,” Southwest DFT Conference, May 2007.

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