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COTS Based High Performance Radar and EW Development Platform

COTS Based High Performance Radar and EW Development Platform. HPEC September 2011 Mikael Taveniku, XCube Gunnar Hillerstrom, Swedish Defence Research Agency. COTS EW/Radar Development Platform. Adarate FPGA Front end & analog interface (ADC/DAC). NVIDIA Floating point DSP & HMI

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COTS Based High Performance Radar and EW Development Platform

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  1. COTS Based High Performance Radar and EW Development Platform HPEC September 2011 Mikael Taveniku, XCube Gunnar Hillerstrom, Swedish Defence Research Agency XCube 2011

  2. COTS EW/Radar Development Platform Adarate FPGA Front end & analog interface (ADC/DAC) NVIDIA Floating point DSP & HMI - GPGPU GTX590 Adapteva (future) Complex CPU/DSPintensive processing - ATDSP (future) / Others - Virtex6 130LXT – 475SXT - 2x National ADC083000 (selectable) - 2x Analog devices AD9739 - 2x 1Gbit Ethernet - PCI-express Data Storage and Control XCube Development Platform - Control / Record / Replay Software - Dual Xeon CPU - Up to 144GByte Memory - >4.4GByte/s Throughput - >8 GByte/s Burst - 96TB removable storage (shown) XCube 2011

  3. Demo Setup (LPI Radar Simulation & Detection) HRFT Standalone Signal Generator Transmit DAC Host Processing 2.4Gsps - 8 bit data 8 Channels 150MHz (I/Q-data) Window FFT waterfall 1200MByte/s throughput (and storage) Control PC Radar (FMCW) / Frequency Hop (FH) External Interfaces Buffering and Processing Disk Manager Other HRFT Internal disk Diskwriter GP-GPU DMA Receiver ADC FPGA Frontend PCIe Disk Scheduler Stream Buffers Interface Manager Processor Array (future FMC) disk Diskwriter Tight Timing Decoupling High Throughput XCube

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