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SGST Preview

SGST Preview. SGST: SiGe Silicon Tracker front end IC. SCIPP, UC Santa Cruz Andrey Martchovsky Gregory Horn Edwin Spencer. Architecture of front end channel: preamp and diffamp.

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SGST Preview

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  1. SGST Preview SGST: SiGe Silicon Tracker front end IC SCIPP, UC Santa Cruz Andrey Martchovsky Gregory Horn Edwin Spencer SGSS front end, Summary August 2008 Edwin Spencer, SCIPP

  2. Architecture of front end channel:preamp and diffamp 118uA 7u 2.4u 11.4u 3.2u 3.2u SGST biases total: 168 uA @ 16.2 pF, 108 uA @ 5.5 pF(900 e-) POWER: 0.202 mW/channel @ 16.2 pF, VT=1fC and 0.130 mW @ 5.5 pF, VT=0.5 fC SGSS front end, Summary August 2008 Edwin Spencer, SCIPP

  3. Shaper schematic 8u 2u 3u SGSS front end, Summary August 2008 Edwin Spencer, SCIPP

  4. Comparator Schematic 10u (digital) SGSS front end, Summary August 2008 Edwin Spencer, SCIPP

  5. SGST Overview • IBM 8WL process, 0.13 mm 8RF CMOS with SiGe 140 Ghz npn added. Submitted using IBM Cadence kit to MOSIS on June 30, 2008. • Circuit development goal: meet SCT 25 ns crossing specs where practical for power minimization. The prototype circuit should be testable for SiGe 8WL radiation evaluation. • Two detector loads simulated, including strays, of 5.5 pF for VT= 1fC and 16 pF for VT = 0.5 fC. This corresponds to 2.5 cm and 10 cm sensor strip length. • Linear regulator included, input 1.4 V, output is 1.2 V for channel. • Bias adjustment for threshold matching skew included, using different strategy than ABCD for lowered power rail. • Resistive front transistor feedback used to reduce npn base shot noise. • Control voltage VSHAPE used to adjust shaping time, +/- 15 % range. SGSS front end, Summary August 2008 Edwin Spencer, SCIPP

  6. SGST Simulated ENC performance 1350 e- @ 16.2 pF 600 nA detector leakage is included. SGSS front end, Summary August 2008 Edwin Spencer, SCIPP

  7. Impulse Response at Comparator 27ns impulse response 5.5 pF Ifront = 100uA, 110uA 16.2 pf Ifront = 170uA, 180 uA, 200 uA SGSS front end, Summary August 2008 Edwin Spencer, SCIPP

  8. AC simulation-phase margin 16.2 pF@120mA 0dB@42Mhz, 57.3° margin 72 degrees phase margin SGSS front end, Summary August 2008 Edwin Spencer, SCIPP

  9. AC simulation-phase margin 16.2 pF @ 150mA 70 degrees @ 150 mA 0 dB@26 Mhz, 66° margin SGSS front end, Summary August 2008 Edwin Spencer, SCIPP

  10. Transient simulation conditions • Nominal bias condition • Detector capacitance default is 16.2 pF, unless otherwise noted • Charge collection time is 10 ns • No parasitic extraction included SGSS front end, Summary August 2008 Edwin Spencer, SCIPP

  11. Diffamp and Shaper Out: 1, 2.8, 4.6, 6.4, 8.2, 10 fC SGSS front end, Summary August 2008 Edwin Spencer, SCIPP

  12. Comparator output: Time Walk (TW) 15.4 ns for 10fC – 1.25 fC span TW (10 – 1.25 fC) =11.9 ns, TW( 10 – 1.02fC) = 17.5 ns SGSS front end, Summary August 2008 Edwin Spencer, SCIPP

  13. Preamp Input impedance for 120 mA bias 220 ohms @ 30 Mhz At 30 Mhz, 322 Ω for 180 uA, 464 Ω for 106 uA SGSS front end, Summary August 2008 Edwin Spencer, SCIPP

  14. Preamp Input impedance for 150 mA bias Drops to 200 ohms with increase of front bias by 25 % At 30 Mhz, 322 Ω for 180 uA, 464 Ω for 106 uA SGSS front end, Summary August 2008 Edwin Spencer, SCIPP

  15. PSRR AC simulation of 3 stages Overall PSRR -7 dB, improved by front cascode -18 dB PSRR (power supply rejection ratio) for shaper_out without regulator filter. SGSS front end, Summary August 2008 Edwin Spencer, SCIPP

  16. Process Monte Carlo: 150 mA bias, 16.2 pf loadVSHAPE= 600 mV Monte Carlo shows guassian process variation, so no bias issues for sample of 500 runs. Final shape is 30.9 ns +/- 2.1 ns. SGSS front end, Summary August 2008 Edwin Spencer, SCIPP

  17. Process Monte Carlo: 150 mA bias, 16.2 pf loadVNcap feedback, VSHAPE= 200 mV For high setting of VSHAPE, peaking time is 28.8 ns, +/- 2.1. SNR is clustered well. SGSS front end, Summary August 2008 Edwin Spencer, SCIPP

  18. Process Monte Carlo: 150 mA bias, 16.2 pf loadVNcap feedback, VSHAPE= 1200 mV For lowest VSHAPE setting, peak is 21.3 ns. SGSS front end, Summary August 2008 Edwin Spencer, SCIPP

  19. Process Monte Carlo: 150 mA bias, 16.2 pf loadMIMcap feedback, VSHAPE= 200 mV Sigma on shape goes to 1.8 ns (from 2.1), a useful improvement by changing feedback cap technology. SGSS front end, Summary August 2008 Edwin Spencer, SCIPP

  20. Process Monte Carlo: 150 mA bias, 16.2 pf loadMIMcap feedback, VSHAPE= 1200 mV SGSS front end, Summary August 2008 Edwin Spencer, SCIPP

  21. SGST progress status COMPLETED • IBM 8WL kit functionality, DRC and LVS and monte carlo. • Channel and bias, simulated with most monte carlo checks done. • Channel laid out on 30 um pitch assembly packing checked. • Linear regulator simulated with monte carlo. NEEDED • Final monte carlo of channel and bias. • Bias circuit layout. • Padframe and protection layout. • Simple serial digital readout design (IBM 8RF digital library in kit and will not need modification). • LVDS driver design and layout. • Submit for MOSIS October 20th 8WL run SGSS front end, Summary August 2008 Edwin Spencer, SCIPP

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