CS 4014 Issues

1. CS 4014 Issues • Both Computer Organization and Operating Systems combined into one course. • Chapters 4, 5 and 6 have a lot of logic circuits that are probably needed for most non-engineering students that eventually take CS 5515, but we will skip for the most part.

2. Preface • One semester covers Ch 1-8 (pg. xx) • Target students: undergraduates in EE, CE or Engineering Science, also CS specialists • Students without a course in digital logic circuits should study Appendix A before course (certainly before Ch. 4)

3. Our Emphasis • High-level block diagrams (e.g., Fig. 4.1, 2, 4, 5, 10, 28 and 31) – Yes, we will cover. • Timing diagrams (e.g., Fig. 4.23, 24) – we will cover a few but not many. • Circuit diagrams (e.g., Fig. 4.6, 7) – we will mostly skip this level.

4. Processor Memory Bus I/O de vice 1 I/O de vice n Figure 4.1. A single-bus structure. Very high level, figure 4.2 is more of the level we need for this chapter

5. Keep referring back to this diagram. This covers the high-level of how printers, CD drives and other I/O devices are connected to the processor and how they communicate both instructions and data.

6. Mo v e #LINE,R0 Initialize memory p oin ter. W AITK T estBit #0,ST A TUS T est SIN. Branc h=0 W AITK W ait for c haracter to b e en tered. Mo v e D A T AIN,R1 Read c haracter. W AITD T estBit #1,ST A TUS T est SOUT. Branc h=0 W AITD W ait for displa y to b ecome ready . Mo v e R1,D A T A OUT Send c haracter to displa y . Mo v e R1,(R0)+ Store c haracter and adv ance p oin ter. Compare #$0D,R1 Chec k if Carriage Return. Branc h 0 W AITK If not, get another c haracter. Mo v e #$0A,D A T A OUT Otherwise, send Line F eed. Call PR OCESS Call a subroutine to pro cess the input line. Figure 4.4 A program that reads one line from the keyboard stores it in memory buffer, and echoes it back to the display. Relate commands to figure 4.2. Move uses address decoder and data lines; Branch, Test use control circuits.

7. High-level graphic depicting different processes as streams of instructions. These streams are frequently interrupted to allow an “interrupt” routine to execute.

8. V dd Processor R I N T R INTR INTR1 INTR2 INTR n Figure 4.6. An equivalent circuit for an open-drain bus used to implement a common interrupt-request line.

9. Figure 4.7. Implementation of interrupt priority using individual interrupt-request and acknowledge lines.

10. OSINIT Set in terrupt v ectors:  Time-slice clo c k SCHEDULER  Soft w are in terrupt OSSER VICES  Keyb oard in terrupts IOData . . . OSSER VICES Examine stac k to determine requested op eration. Call appropriate routine. SCHEDULER Sa v e program state. Select a runnable pro cess. Restore sa v ed con text of new pro cess. Push new v alues for PS and PC on stac k. Return from in terrupt. (a) OS initialization, services, and scheduler IOINIT Set pro cess status to Blo c k ed. Initialize memory buffer address p oin ter and coun ter. Call device driv er to initialize device and enable in terrupts in the device in terface. Return from subroutine. IOD A T A P oll devices to determine source of in terrupt. Call appropriate driv er. If END = 1, then set pro cess status to Runnable. Return from in terrupt. (b) I/O routines KBDINIT Enable in terrupts. Return from subroutine. KBDD A T A Chec k device status. If ready , then transfer c haracter. If c haracter = CR, then { set END = 1; Disable in terrupts } else set END = 0. Return from subroutine. (c) Keyboard driver Figure 4.10. A few operating system routines.

13. Compare to the high level figure 4.2 and identify components.

14. Again, compare to the high level figure 4.2 and identify components