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Day6: January 23, 2000 Control Hazards (Pipelined ISA)

CS184b: Computer Architecture [Single Threaded Architecture: abstractions, quantification, and optimizations]. Day6: January 23, 2000 Control Hazards (Pipelined ISA). Today. Control Hazards Techniques to reduce impact Exception what why challenges. Last Time. Pipelining

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Day6: January 23, 2000 Control Hazards (Pipelined ISA)

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  1. CS184b:Computer Architecture[Single Threaded Architecture: abstractions, quantification, and optimizations] Day6: January 23, 2000 Control Hazards (Pipelined ISA) Caltech CS184b Winter2001 -- DeHon

  2. Today • Control Hazards • Techniques to reduce impact • Exception • what • why • challenges Caltech CS184b Winter2001 -- DeHon

  3. Last Time • Pipelining • Cycles in flow graph • Avoiding • or accommodating dynamically Caltech CS184b Winter2001 -- DeHon

  4. Hazards • Structural (resource bound) • Data (value timing) • Control (knowing where to go next) Caltech CS184b Winter2001 -- DeHon

  5. Pipeline DLX DLX pipelined datapath from H&P (Fig. 3.4) Caltech CS184b Winter2001 -- DeHon

  6. Data Hazards • Didn’t effect IF or ID • Worst-case, one cycle stall Caltech CS184b Winter2001 -- DeHon

  7. Pipeline DLX DLX pipelined datapath from H&P (Fig. 3.4) Caltech CS184b Winter2001 -- DeHon

  8. Control Hazard IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB Caltech CS184b Winter2001 -- DeHon

  9. Control Hazard IF ID EX MEM WB IF ID EX MEM WB Caltech CS184b Winter2001 -- DeHon

  10. What can we do? Caltech CS184b Winter2001 -- DeHon

  11. What can we do? • Move earlier • tighten cycle • “Guess” direction • predict (and squash) • Accepted delayed transfer as part of arch. • Branch delay slot Caltech CS184b Winter2001 -- DeHon

  12. Revised Pipeline DLX repipelined datapath from H&P (Fig. 3.22) Caltech CS184b Winter2001 -- DeHon

  13. Consequence? IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB Caltech CS184b Winter2001 -- DeHon

  14. Consequence • Smaller cycle • Longer ID stage delay • Need separate Adder • Not branch to reg.? Caltech CS184b Winter2001 -- DeHon

  15. Pipeline IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB Caltech CS184b Winter2001 -- DeHon

  16. Avoiding Lost Cycles • Do know where to go in not-taken case • just keep incrementing PC • “Guess” taken • Begin Executing • Squash if Wrong Caltech CS184b Winter2001 -- DeHon

  17. Predict Branch Taken Branch: IF ID EX MEM WB Branch+1: IF ID EX MEM WB Branch+2: IF ID EX MEM WB IF ID EX MEM WB Caltech CS184b Winter2001 -- DeHon

  18. Predict Branch Taken (not) Branch: IF ID EX MEM WB Branch+1: IF ID -- -- -- Branch+2: IF ID EX MEM WB IF ID EX MEM WB Squash ok: no state change, no effect of exec op Caltech CS184b Winter2001 -- DeHon

  19. Avoiding Lost Cycle (2) • Solve like load latency • separate load request • from load use • Separate branch instruction (computation) • From branch effect • Architecturally specify • branch not take effect until X cycles later Caltech CS184b Winter2001 -- DeHon

  20. Branch Delay Slot • SUB R1,R2,R3 • BEQZ R1,exit • ADD R4,R5,R6 // always executed • SUB R1,R4,R3 • exit: • SW R3,4(R11) Caltech CS184b Winter2001 -- DeHon

  21. Branch Taken Branch: IF ID EX MEM WB B-Delay: IF ID EX MEM WB Target : IF ID EX MEM WB IF ID EX MEM WB Caltech CS184b Winter2001 -- DeHon

  22. Branch Not Taken Branch: IF ID EX MEM WB B-Delay: IF ID EX MEM WB Branch+2: IF ID EX MEM WB IF ID EX MEM WB Caltech CS184b Winter2001 -- DeHon

  23. More Control Fun to Come... • Knowing what to run next can be big limit to exploiting parallelism (deep pipelining) • ILP need more branch prediction Caltech CS184b Winter2001 -- DeHon

  24. Exceptions Caltech CS184b Winter2001 -- DeHon

  25. What? • Control transfer away from “normal” execution • Every instruction • a conditional, multiway branch? • (branch and link) Caltech CS184b Winter2001 -- DeHon

  26. What (examples) • Page Fault • System call • Interrupt (event) • io • timer • Unknown Instruction Caltech CS184b Winter2001 -- DeHon

  27. Why? • Cases represented are uncommon • Instructions explicitly checking for cases add cycles • …lots of cycles to check all cases • when seldom occur • Long instructions to describe all ways can branch • more compact to “configure” implicit places to go Caltech CS184b Winter2001 -- DeHon

  28. Properties/Types • synch/Asynch • request/coerced • maskable? • within/between instructions • resume/terminate Caltech CS184b Winter2001 -- DeHon

  29. How make implementation difficult? • Need to preserve sequential instruction abstraction • Creates cause to see what happens between instructions • need to provide clean state view • Instruction fail and need to be “restarted” • e.g. page fault Caltech CS184b Winter2001 -- DeHon

  30. Hard cases • Synchronous • within instruction • restartable • latencies or parallelism allow out-of-order completion Caltech CS184b Winter2001 -- DeHon

  31. Hazards • LW R1,4(R2) • ADD R3,R4,R3 • Case: • DLX • Pipeline where WB can occur before MEM • May be correct to complete ADD • no hazards • but not restartable when fault on LW address Caltech CS184b Winter2001 -- DeHon

  32. Restart Hazards • LW R1,4(R2) • ADD R3,R4,R3 • Restart/rerun • can get wrong answer by executing instruction again Caltech CS184b Winter2001 -- DeHon

  33. Next Time • Talk about how to solve • (read Smith/Imprecise exception paper) • …and get started in ILP • note: read tomasulo along with HP4.2 Caltech CS184b Winter2001 -- DeHon

  34. Big Ideas • Maintaining Abstraction • Challenge of deciding what to do next • cyclic dependency • Minimizing cost thereof • pipeline structure (minimize latency) • branch delay • prediction • Common Case • exceptions • control flow Caltech CS184b Winter2001 -- DeHon

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