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Advanced Encryption Standard For Smart Card Security. Aiyappan Natarajan David Jasinski Kesava R.Talupuru Lilian Atieno Advisor: Prof. Wayne Burleson. Outline. Introduction System Architecture Encryption Decryption Goals Work Plan & Schedule. Introduction.
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Advanced Encryption StandardFor Smart Card Security Aiyappan Natarajan David Jasinski Kesava R.Talupuru Lilian Atieno Advisor: Prof. Wayne Burleson
Outline • Introduction • System Architecture • Encryption • Decryption • Goals • Work Plan & Schedule
Introduction • Security in Smart Cards - Cryptography • Applications • Identification Cards • Credit Cards • Algorithms Used • Rijndael • DES(Data Encryption Standard) • RSA(Ronald, Samir and Adleman)
Overall Block Diagram ISA Reset clk Processor FSM Req I/P I/P FSM Ready I/P Reset clk clk I/P Key 256 Encrypt Key Sched 16 Sub key clk 256 O/P FSM Reset 16 O/P Ready O/P Request O/P
Encryption • Sub Bytes( ) Transformation • Shift Rows( ) Transformation • Mix Columns( ) Transformation • Add Round Key( ) Transformation • Key Expansion
Encryption Algorithm Flow Raw Data Sub Key Key Add Substitution Shift Row Mix Column Key Add Sub Key Repeat (Round-1) times ED Key Add Shift Row Substitution Sub Key
Decryption • Inverse Shift Rows( )Transformation • Inverse Sub Bytes( )Transformation • Add Round Key( )Transformation • Inverse Mix Columns( )Transformation
Goals • Hardware Implementation of the Rijndael algorithm using Verilog HDL • Functional Verification of the code with the help of the available test vectors • Synthesis of Verilog Code • Verification of the functionality of the synthesized structure • Speed and Area Estimations
Work Plan & Schedule • Kesava & Lilian – Encryption & Decryption Core • David – Key Expansion Module • Aiyappan – I/P & O/P Controller, Processor FSM • Behavioral Model – March 10th • RTL model – April 20th • Synthesis – April 30th • Verification – May 15th
References • Draft of AES - Federal Information Processing Standards Publication, Washington D.C. • Kuo, Henry and Ingrid Verbauwhede- Architectural Optimization for a 1.82Gbits/sec VLSI implementation of the AES Rijndael Algorithm • Rankl and W.Effing- Smart Card Handbook, Second Edition, Chichester, England, John Wiley & Sons Ltd.,2000