Some Definitions

1. Some Definitions • Combinational logic: a digital logic circuit in which logical decisions are made based only on combinations of the inputs (e.g., an adder). • Sequential logic: a circuit in which decisions are made based on combinations of the current inputs as well as the past history of inputs (e.g., a memory unit). • Finite state machine: a circuit which has an internal state, and whose outputs are functions of both current inputs and its internal state (e.g., a vending machine controller).

2. i f 0 0 i f C o m b i n a t i o n a l 1 1 l o g i c u n i t . . . . . . i f n m The Combinational Logic Unit • Translates a set of inputs into a set of outputs according to one or more mapping functions. • Inputs and outputs for a CLU normally have two distinct (binary) values: high and low, 1 and 0, 0 and 1, or 5 v and 0 v, for example. • The outputs of a CLU are strictly functions of the inputs, and the outputs are updated immediately after the inputs change. A set of inputs i0–in are presented to the CLU, which produces a set of outputs according to mapping functions f0–fm. Fig A.1

3. L i g h t Z “Hot” G N D S w i t c h A S w i t c h B Truth Tables • Developed in 1854 by George Boole • Further developed by Claude Shannon (Bell Labs) • Outputs are computed for all possible input combinations (how many input combinations are there? Consider a room with two light switches. How must they work†? Fig. A.2 I n p u t s O u t p u t A B Z 0 0 0 0 1 1 1 0 1 1 1 0 †Don't show this to your electrician, or wire your house this way. This circuit definitely violates the electric code. The practical circuit never leaves the lines to the light "hot" when the light is turned off. Can you figure how?

4. Fig A.4 Truth Tables Showing All Possible Functions of Two Binary Variables • The more frequently used functions have names: AND, XOR, OR, NOR, XOR, and NAND. (Always use upper-case spelling.)

5. A B F A B F 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 1 0 1 1 1 1 1 1 1 A A F = A B F = A + B B B A N D O R A F A F 0 0 0 1 1 1 1 0 A F = A A F = A B u f f e r N O T ( I n v e r t e r ) Logic Gates and Their Symbols Fig. A.5 Logic Gate Symbols for AND, OR, Buffer, and NOT Boolean functions • Note the use of the “inversion bubble.” • Be careful about the “nose” of the gate when drawing AND vs. OR.

6. A B F A B F 0 0 1 0 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 1 1 0 A A F = A B F = A + B B B N A N D N O R A B F A B F 0 0 0 0 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 1 1 1 A A + F = A B F = A B B B E x c l u s i v e - O R ( X O R ) E x c l u s i v e - N O R ( X N O R ) Fig A.6 Logic Gate Symbols for NAND, NOR, XOR, and XNOR Boolean functions

7. Fig A.7 Variations of Basic Logic Gate Symbols (a) 3 inputs (b) A negated input (c) Complementary outputs

8. Fig A.9 Assignments of Logical 0 and Logical 1 to Voltage Ranges + 5 V + 5 V L o g i c a l 1 L o g i c a l 1 2 . 4 V 2 . 0 V F o r b i d d e n r a n g e F o r b i d d e n r a n g e 0 . 8 V L o g i c a l 0 0 . 4 V 0 V 0 V L o g i c a l 0 (a) At the output of alogic gate (b) At the input to alogic gate

9. Tbl A.1 The Basic Properties of Boolean Algebra Principle of duality:The dual of a Boolean function is gotten by replacing AND with OR and OR with AND, constant 1s by 0s,and 0s by 1s Postulates Theorems

10. A B A B = A + B A + B = A B Fig A.11 0 0 1 1 1 1 0 1 1 1 0 0 1 0 1 1 0 0 1 1 0 0 0 0 D e M o r g a n ’s t h e o r e m : A + B = A + B = A B Fig A.12 A A F = A + B F = A B B B DeMorgan’s Theorem Discuss: Applying DeMorgan’s theorem by “pushing the bubbles” and “bubble tricks.”

11. Fig A.16 Four Notations Used at Circuit Intersections

12. Positive versus Negative Logic • Positive logic: truth, or assertion is represented by logic 1, higher voltage; falsity, de- or unassertion, logic 0, is represented by lower voltage. • Negative logic: truth, or assertion is represented by logic 0 , lower voltage; falsity, de- or unassertion, logic 1, is represented by lower voltage

13. Digital Components • High-level digital circuit designs are normally made using collections of logic gates referred to as components, rather than using individual logic gates. The majority function can be viewed as a component. • Levels of integration (numbers of gates) in an integrated circuit (IC): • Small-scale integration (SSI): 10–100 gates. • Medium-scale integration (MSI): 100–1000 gates. • Large-scale integration (LSI): 1000–10,000 logic gates. • Very large scale integration (VLSI): 10,000–upward. • These levels are approximate, but the distinctions are useful in comparing the relative complexity of circuits. • Let us consider several useful MSI components.

14. S N 7 4 0 0 Q U A D R U P L E 2 - I N P U T P O S I T I V E - N A N D G A T E S d e s c r i p t i o n T h e s e d e v i c e s c o n t a i n f o u r i n d e p e n d e n t s c h e m a t i c ( e a c h g a t e ) 2 - i n p u t N A N D g a t e s . V C C f u n c t i o n t a b l e ( e a c h g a t e ) p a c k a g e ( t o p v i e w ) 4 k  1 . 6 k  1 3 0  I N P U T S O U T P U T 1 A V 1 1 4 C C 1 B 4 B A B Y 2 1 3 1 Y 4 A 3 1 2 H H L A 2 A 4 Y 4 1 1 2 B 3 B L X H 5 1 0 B 2 Y 3 A 6 9 X L H G N D 3 Y 7 8 Y a b s o l u t e m a x i m u m r a t i n g s S u p p l y v o l t a g e , V C C 7 V I n p u t v o l t a g e : 5 . 5 V 1 k  O p e r a t i n g f r e e - a i r t e m p e r a t u r e r a n g e : 0 ° C t o 7 0 ° C S t o r a g e t e m p e r a t u r e r a n g e – 6 5 ° C t o 1 5 0 ° C G N D r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s M I N N O M M A X U N I T l o g i c d i a g r a m ( p o s i t i v e l o g i c ) V S u p p l y v o l t a g e 4 . 7 5 5 5 . 2 5 V 1 A C C 1 Y 1 B V H i g h - l e v e l i n p u t v o l t a g e 2 V I H 2 A 2 Y 2 B V L o w - l e v e l i n p u t v o l t a g e 0 . 8 V I L 3 A 3 Y 3 B I H i g h - l e v e l o u t p u t c u r r e n t – 0 . 4 m A O H 4 A 4 Y I L o w - l e v e l o u t p u t c u r r e n t 1 6 m A 4 B O L Y = A B T O p e r a t i n g f r e e - a i r t e m p e r a t u r e 0 7 0 ° C A e l e c t r i c a l c h a r a c t e r i s t i c s o v e r r e c o m m e n d e d o p e r a t i n g f r e e - a i r t e m p e r a t u r e r a n g e V A L U E O P E R A T I N G C O N D I T I O N S M I N T Y P M A X U N I T V V V = M I N , V = 0 . 8 V , I = – 0 . 4 m A 2 . 4 3 . 4 O H C C I L O H V V V = M I N , V = 2 V , I = 1 6 m A 0 . 2 0 . 4 O L C C I H O L I V = M A X , V = 2 . 4 V  A 4 0 I H C C I I V = M A X , V = 0 . 4 V m A – 1 . 6 I L C C I I V = M A X , V = 0 V m A 4 8 C C H C C I I V = M A X , V = 4 . 5 V m A 1 2 2 2 C C L C C I s w i t c h i n g c h a r a c t e r i s t i c s , V = 5 V , T = 2 5 ° C C C A P A R A M E T E R F R O M ( i n p u t ) T O ( o u t p u t ) T E S T C O N D I T I O N S M I N N O M M A X U N I T t 1 1 2 2 n s R = 4 0 0  P L H L A o r B Y C = 1 5 p F t 7 1 5 n s L P H L Fig A.20 Simplified Data Sheet

15. The MultiplexerFig A.21 Block Diagram and Truth Table D 0 0 s t 0 A B F u p D 0 1 n 1 i F a 0 0 D D 1 0 t 0 2 a D 0 1 D D 1 1 1 3 1 0 D 2 1 1 D 3 A B C o n t r o l i n p u t s F = A B D + A B D + A B D + A B D 0 1 2 3 Fig A.22 AND-OR Circuit Implementation

16. F 0 0 D A B F F F F 0 0 1 2 3 F 0 1 1 D 0 0 0 0 0 0 0 F 1 0 2 0 0 1 0 0 0 0 F 1 1 3 0 1 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 1 0 0 0 A B 1 0 1 0 1 0 0 1 1 0 0 0 1 0 F = D A B F = D A B 0 2 1 1 1 0 0 0 1 F = D A B F = D A B 1 3 The Demultiplexer (DEMUX) Fig A.25 Block Diagram and Truth Table

17. Fig A.32 A Programmable Logic Array • A PLA is a customizable AND matrix followed by a customizable OR matrix

18. Fig A.33 Simplified Representation of a PLA

19. Speed and Performance • The speed of a digital system is governed by • the propagation delay through the logic gates and • the propagation across interconnections.

20. T r a n s i t i o n t i m e + 5 V ( F a l l t i m e ) 1 0 % T h e N O T g a t e 5 0 % i n p u t c h a n g e s ( 2 . 5 V ) f r o m 1 t o 0 9 0 % 0 V P r o p a g a t i o n d e l a y ( L a t e n c y ) T r a n s i t i o n t i m e + 5 V ( R i s e t i m e ) 9 0 % T h e N O T g a t e 5 0 % o u t p u t c h a n g e s ( 2 . 5 V ) f r o m 0 t o 1 1 0 % 0 V T i m e Fig A.47 Propagation Delay for a NOT Gate (Adapted from Hamacher et al., 1990)

21. Fan-in May Affect Circuit Depth Fig A.49 A Logic Gate

22. Sequential Logic • The combinational logic circuits we have been studying so far have no memory. The outputs always follow the inputs. • There is a need for circuits with a memory, which behave differently depending upon their previous state. • An example is the vending machine, which must remember how many and what kinds of coins have been inserted, and which behave according to not only the current coin inserted, but also upon how many and what kind of coins have been deposited previously. • These are referred to as finite state machines, because they can have at most a finite number of states.

23. i f o o O u t p u t s I n p u t s i C o m b i n a t i o n a l f k m l o g i c u n i t S t a t e b i t s Q D 0 0 s 0 Q D n n s n S y n c h r o n i z a t i o n s i g n a l D e l a y e l e m e n t s ( o n e p e r s t a t e b i t ) Fig A.50 Classical Model of a Finite State Machine . . . . . . . . . . . . . . .

24. 1 A 0 1 B A   0 A + B B 1 A + B 0   T i m i n g b e h a v i o r A.51 A NOR Gate with a Lumped Delay This delay between input and output is at the basis of the functioning of an important memory element, the flip-flop.

25. S Q S R Q t t t i + 1 0 0 0 0 R S 0 0 1 0 Q 0 1 0 1 Q 0 1 1 ( d i s a l l o w e d ) 1 0 0 1 Q Q 1 0 1 0 R     1 1 0 1 1 1 1 ( d i s a l l o w e d ) 2   2   T i m i n g b e h a v i o r A.52 An S-R Flip-Flop The S-R flip-flop is an active-high (positive logic) device.

26. Fig A.53 Converting a NOR S-R to an NAND S-R Active-high NOR Implementation Push bubbles (DeMorgan’s) Rearrange bubbles Convert from bubbles to active-low signal names

27. Fig A.55 A Clock Waveform In a positive logic system, the “action” happens when the clock is high, or positive. The low part of the clock cycle allows propagation between subcircuits, so their inputs are stable at the correct value when the clock next goes high.

28. S R S Q C L K C L K Q Q R Q 2   3   T i m i n g b e h a v i o r A.56 A Clocked S-R Flip-Flop The clock signal, CLK, turns on the inputs to the flip-flop.

29. C i r c u i t D D Q C L K C L K Q Q Q     D Q 2   2   S y m b o l C Q T i m i n g b e h a v i o r Fig A.57 A Clocked D (Data) Flip-Flop The clocked D flip-flop, sometimes called a latch, has a potential problem: If D changes while the clock is high, the output will also change. The Master-Slave flip-flop solves this problem.

30. C i r c u i t D M a s t e r S l a v e D D Q D Q M S C L K Q C L K C C Q M S Q S Q D Q S     S y m b o l 3   2   2   2   Q T i m i n g b e h a v i o r A.58 A Master-Slave Flip-Flop The rising edge of the clock clocks new data into the master, while the slave holds previous data. The falling edge clocks the new master data into the slave.

31. Fig A.59 The Basic J-K Flip-Flop • The J-L flip-flop eliminates the S = R = 1 problem of the S-R flip-flop, because Q enables J while Q' disables K, and vice versa. • However there is still a problem. If J goes momentarily to 1 and then back to 0 while the flip-flop is active and in the reset, the flip-flop will “catch” the 1. • This is referred to as “1’s catching.” • The J-K master-slave flip-flop solves this problem.

32. Fig A.61 A Master-Slave J-K Flip-Flop

33. S t o r e s D R Q C L K Q S M a i n l a t c h D S t o r e s D Fig A.62 Negative Edge-Triggered D Flip-Flop • When the clock is high, the two input latches output 0, so the main latch remains in its previous state regardless of changes in D. • When the clock goes high-low, values in the two input latches will affect the state of the main latch. • While the clock is low, D cannot affect the main latch. e d u t i l p m A T i m e C y c l e t i m e = 2 5 n s

34. T i m e ( t ) 4 3 2 1 0 4 3 2 1 0 T i m e ( t ) q R E S E T 0 0 0 0 1 0 1 1 0 0 0 q 0 1 0 1 0 3 - b i t 1 s y n c h r o n o u s s D Q 0 c o u n t e r s 0 s D Q 1 Q s 1 Q C L K Finite State Machine Design • Counter has a clock input, CLK, and a RESET input. • Has two output lines, which must take values of 00, 01, 10, and 11 on subsequent clock cycles. Fig A.63 A Modulo-4 Counter It requires two flip-flops to store the state.

35. 0 0 0 x 0 1 4 - t o - 1 z D Q 0 M U X 1 0 1 s 0 1 1 Q 0 0 0 1 4 - t o - 1 z D Q M U X 1 1 0 s 1 1 1 Q Mealy versus Moore Machines • Moore model: Outputs are functions of present state only. • Mealy model: Outputs are functions of inputs and present state. • Previous FSM designs were Mealy machines, because next state was computed from present state and inputs. x z 2 1 z x 5 x 5 1 0 z P L A 0 Q D s 0 C L K C L K Q D s • Both are equally powerful. 1

36. Fig A.78 A 4-Bit Register Gate-Level View Fig A.79 Abstract Representation of a 4-Bit Register Chip-Level View

37. c 1 c 0 D D D D 2 3 1 0 L e f t s h i f t o u t R i g h t s h i f t i n L e f t s h i f t i n D Q D Q D Q D Q R i g h t s h i f t o u t c 0 c C L K 1 E n a b l e ( E N ) Q Q Q Q 3 2 1 0 C o n t r o l F u n c t i o n c c 1 0 L e f t s h i f t i n D D D D 3 2 1 0 0 0 N o c h a n g e L e f t s h i f t o u t R i g h t s h i f t o u t 0 1 S h i f t l e f t R i g h t s h i f t i n c Q Q Q Q 0 1 0 S h i f t r i g h t c 3 2 1 0 1 1 1 P a r a l l e l l o a d Fig A.80 Internal Layout and Block Diagram for Left-Right Shift with Parallel Read/Write Capabilities

38. Fig A.81 A Modulo(8) Ripple Counter Note the use of the T flip-flops. They are used to toggle the input of the next flip-flop when its output is 1.