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Digital Logic Design CSE-241

Digital Logic Design CSE-241. Unit 16. Clocked Latch (flip-flop):. A flip-flop differs from a latch in the manner it changes states. A flip-flop is a clocked device, in which only the clock edge determines when a new bit is entered.

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Digital Logic Design CSE-241

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  1. Digital Logic DesignCSE-241 Unit 16

  2. Clocked Latch (flip-flop): • A flip-flop differs from a latch in the manner it changes states. A flip-flop is a clocked device, in which only the clock edge determines when a new bit is entered. • A clock is a free-running signal with a fixed cycle time (clock period). Clocks are used in digital circuits to give synchronization between different circuits. In the clocked latches the outputs change states as per the inputs only on the occurrence of a clock pulse. Muhammad Usman Arif

  3. CLOCKED R-S FLIP-FLOP WITH ACTIVE HIGH INPUT Muhammad Usman Arif

  4. CLOCKED R-S FLIP-FLOP WITH ACTIVE LOW INPUT • The basic latch is the same • When the clock signal is HIGH, the two NAND gates are enabled and the S and R inputs are passed on to flip-flop inputs with their status complemented. The outputs can now change states as per the status of R and S at the flip-flop inputs.  Muhammad Usman Arif

  5. Level-Triggered and Edge-Triggered Flip-Flops: • In a level-triggered flip-flop, the output responds to the data present at the inputs during the time the clock pulse level is HIGH (or LOW). • In case of an edge-triggered flip-flop the flip-flop responds to the input only on a transition of the clock pulse. • It could be a HIGH-to-LOW or a LOW-to-HIGH transition of the clock signal. The flip-flop in the two cases is referred to as • positive edge-triggered • negative edge triggered respectively. • Any changes in the input during the time the clock pulse is HIGH (or LOW) do not have any effect on the output. • In the case of an edge-triggered flip-flop, an edge detector circuit transforms the clock input into a very narrow pulse that is a few nanoseconds wide. This pulse is so narrow that the operation of the flip–flop can be considered to have occurred on the edge itself. Muhammad Usman Arif

  6. EDGE TRIGGERED R-S FLIP-FLOP The triangle points that its is a dynamic input clock. Which means the flip flop works on the edge of the clock Muhammad Usman Arif

  7. Positive Edge-Triggered Circuit: Muhammad Usman Arif

  8. Edge Triggered D-flip flop • The truth tables for positive and negative edge triggered D-flip flops are shown below. Muhammad Usman Arif

  9. J-K Flip-Flop • A J-K flip-flop behaves in the same fashion as an R-S flip-flop except for one of the entries in the function table. • In the case of an R-S flip-flop, the input combination S = R = 1 is prohibited. In the case of a J-K flip-flop with active HIGH inputs, the output of the flip-flop toggles, that is, it goes to the other state, for J = K = 1 . The output toggles. • Thus, a J-K flip-flop overcomes the problem of a forbidden input combination of the R-S flip-flop. • This is achieved by a minor addition in the R-S flip flop circuit. • Notice in the figure that the output is connected back to the input of gate G2. and the output is connected back to the input of gate G1.  Muhammad Usman Arif

  10. J-K Flip-Flop Muhammad Usman Arif

  11. Q Q J Example CLK Determine the Q output for the J-K flip-flop, given the inputs shown. K Notice that the outputs change on the leading edge of the clock. Solution Set Toggle Set Latch CLK J K Q Muhammad Usman Arif

  12. D-flip-flop Toggle mode • A D-flip-flop does not have a toggle mode like the J-K flip-flop, but you can hardwire a toggle mode by connecting Q back to D as shown. This is useful in some counters as you will see in later. • For example, if Q is LOW, Q is HIGH and the flip-flop will toggle on the next clock edge. Because the flip-flop only changes on the active edge, the output will only change once for each clock pulse. Muhammad Usman Arif

  13. J-K Flip-Flop with PRESET and CLEAR Inputs: • It is often necessary to clear a flip-flop to a logic ‘0’ state (Qn = 0) or preset it to a logic ‘1’ state (Qn =1 ). • both PRESET and CLEAR inputs should not be made active at the same time.  Muhammad Usman Arif

  14. J-K Flip-Flop with PRESET and CLEAR Inputs: • It is often necessary to clear a flip-flop to a logic ‘0’ state (Qn = 0) or preset it to a logic ‘1’ state (Qn =1 ). • both PRESET and CLEAR inputs should not be made active at the same time.  Muhammad Usman Arif

  15. PRE Q CLR PRE Example Q J CLK Determine the Q output for the J-K flip-flop, given the inputs shown. K Solution CLR Set Toggle Set Reset Toggle Latch CLK J K Set Reset Q Muhammad Usman Arif

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