VLSI Testing and Verification

VLSI Testing and Verification Shmuel Wimer Bar Ilan University, School of Engineering

Design for Testability • Testability requires design to be: • Controllable: set to 1 and reset to 0 every circuit node • Observable: be able to examine the logic value of any circuit node • It reduces testing cost • allows high fault coverage with relatively few test vectors • Essential to silicon debug since probing every node is impossible • There are two design for testability (DFT) methods: • Scan-based design • Built-in self-test (BIST)

Clock Scan Mode Scan-in 1 Q Flip-flop 0 Data-in Scan-Chain Flip-Flop When scan mode is 0 the D flip-flop behaves in ordinary mode, and input is being read from data-in. When scan mode is 1 input is taken from scan-in. All the flip-flops are then serially connected from Q to data-in, a giant shift register, spanning the whole chip. In scan mode all the inputs of flip-flops can be set by streaming in their desired values. Similarly, the output of flip-flops can be streamed out.

Scan-in Outputs Combinational Logic Cloud Combinational Logic Cloud Inputs FF FF FF FF FF FF FF FF FF FF FF FF Scan-out Scan-Chain Connections

VLSI Testing and Verification

VLSI Testing and Verification

Presentation Transcript

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