Chapter 3

1. Chapter 3 • How transistors operate and form simple switches • CMOS logic gates • PLA, PAL, FPGA • Basic electrical characteristics of logic circuits

2. Transistor Switches • Logic Circuits are built with Transistors • “A full treatment of transistor behavior is beyond the scope of this text” • MOSFETs • NMOS - nchannel • PMOS – pchannel

3. NMOS vs PMOS x = "high" x = "low" x = "low" x = "high" (a) A simple switch controlled by the input x (a) A switch with the opposite behavior Gate Gate Source Drain Drain Source V Substrate (Body) DD Substrate (Body) (b) PMOS transistor (b) NMOS transistor V V G G V V V V S D S D (c) Simplified symbol for an NMOS transistor (c) Simplified symbol for a PMOS transistor

4. NMOS & PMOS in Logic Circuits V V = 0 V V D D D V G V = 0 V S Closed switch Open switch when V = V when V = 0 V G DD G (a) NMOS transistor V = V V V S DD DD DD V G V V V = V D D D DD Open switch Closed switch when V = V when V = 0 V G DD G (b) PMOS transistor

5. NMOS Inverter V DD R R + 5 V V V - f f V V x x (a) Circuit diagram (b) Simplified circuit diagram x f x f (c) Graphical symbols

6. NMOS NAND vs AND V V V DD DD DD V V f f V x 1 A x x f V 1 2 x 1 0 0 1 x x f V 1 2 x 0 1 1 2 0 0 0 1 0 1 V x 2 0 1 0 1 1 0 1 0 0 1 1 1 (a) Circuit (b) Truth table (b) Truth table (a) Circuit x x 1 1 x x 1 f f 1 f f x x x x 2 2 2 2 (c) Graphical symbols (c) Graphical symbols

7. NOR and OR What would an OR gate look like?

8. SN7408 - QUADRUPLE 2-INPUT POSITIVE-AND GATES

9. What’s Wrong With this Picture? V DD R V f V x When Vx is high there is a constant current through R

10. Structure of an NMOS Circuit V DD V f V x 1 V x 2

11. Structure of a CMOS circuit

12. V DD T 1 V V x f T 2

14. Vf Vf = X1X2 = X1 + X2 Vf = X1X2 PUN = Vf PDN = Vf

15. f = X1 + X2X3

16. Types of Integrated Circuits • Standard Logic • Programmable Logic • Custom Logic

17. 7400 Series Standard Chips - random logic V DD 7404 7408 7432 x 1 x 2 x 3 = x1x2 + x2x3 f

18. Standard Logic • Seldom used – with exception of buffers • SSI • Earliest devices only a few logic gates/transistors • MSI • 10 to100 gates • LSI • Greater than MSI • VLSI

19. PLDs – Programmable Logic Devices } • PLA – Programmable Logic Array • PAL – Programmble Array Logic • CPLD – Complex PLD • FPGA – Field Programmable Gate Arrays • Custom Chips • ASIC – Application Specific Integrated Circuit • Gate Arrays • Memory SPLDs

20. PLA – Programmable Logic Array • Based on the idea that logic functions can be realized in SoP form • “Modest” size circuits • Inputs & Outputs of not more than 32

21. x x x 1 2 3 Programmable connections OR plane P 1 P 2 P 3 P 4 AND plane f f 1 2

22. x x x 1 2 3 Programmable connections OR plane P 1 P 2 P 3 P 4 f1 = x1x2 + x1x3 + x1x2x3 AND plane f2 = x1x2 + x1x2x3 + x1x2 f f 1 2

23. x x x 1 2 3 OR plane P 1 P 2 P 3 P 4 AND plane f f 1 2

24. PAL – Programmble Array Logic • PLA’s Programmable Fuses • Fabrication difficult • Fuses slow down circuit • PALs • Only AND plane is programmable • OR plane is fixed • “Modest” size circuits • Inputs & Outputs of not more than 32

25. x x x 1 2 3 P 1 f 1 P 2 P 3 f 2 P 4 AND plane

26. PAL Macrocell Select Enable f 1 Flip-flop D Q Clock To AND plane

27. CPLD – Complex PLD • Multiple Circuit blocks on a single chip • Each circuit block similar to PAL or PLA • Typical CPLDs • 16 Macro cells in each PAL like block • 5 to 20 inputs to each OR gate • 2 to more than 100 PAL like blocks

28. PAL-like PAL-like I/O block I/O block block block Interconnection wires PAL-like PAL-like I/O block I/O block block block Structure of a complex programmable logic device (CPLD).

29. Note how output pin can be used as an input pin but associated macrocell cannot be used – some CPLDs include additional wiring to get around this limitation A section of a CPLD

30. Equivalent Gates • Two input NAND gate used as measure of circuit size • SPLD, CPLD macrocell = 20 Equivalent Gates • PAL with 8 Macrocells can hold circuit of about 160 EG • CPLD with 500 macrocells can hold circuit of about 10,000 EG • Today’s logic circuits demand circuits greater than 10,000 EG

31. Memory as Logic Address • How Memory Works • Supply address • Get Data Data

32. Memory as Logic Address • Consider an 8 location memory chip with one binary bit at each location • How many bits to address a location? • How many bits at each location? Data

33. Memory as Logic Address A2 A1 A0 Data 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 0 Data f= A2A1A0 + A2A1A0 What would you name this?

34. FPGA – Field Programmable Gate Arrays • Quite different from SPLDs and CPLDs • FPGAs don’t have AND or OR planes • Logic blocks – most common are LUTs • I/O blocks • Interconnection wires • Greater than 1M EG

37. x x 2 1 0/1 0/1 0/1 0/1 f 0/1 0/1 0/1 0/1 x 3 A three-input LUT.

38. Select Out Flip-flop In 1 In D Q LUT 2 In 3 Clock Inclusion of a flip-flop in an FPGA logic block.

39. A section of a programmed FPGA.

40. Custom Chips, Standard Cells, & Gate Arrays • Programmable switches • Size issue • Speed issue

41. Custom Chips • Complete flexibility in transistor placement and connection • Large design effort • Large cost • Large quantities

42. ASICsApplication Specific Integrated Circuits • Standard Cell Libraries • Configurable connections

43. Gate Arrays • Gates prefabricated • Connections added later

44. In-System Programmingvs? Out of System Programming • Compare Teensy++ to ATtiny261

45. Programming • PALs & PLAs usually programmed out of systems • CPLDs usually programmed via JTAG in-system • FPGAs programmed via JTAG in-system • PALs, PLAs, & CPLDs nonvolatile • FPGAs volatile

46. Practical Aspects • Transistor Operation • Static Operation - Voltage Levels • Dynamic Operation – Transition Times • Power Dissipation

47. I D Triode Saturation 0 V – V GS T V DS The current-voltage relationship in the NMOS transistor.

48. V V D D V G V = 0 V S Open switch when V = 0 V G

49. V V = 0 V D D V G V = 0 V S Closed switch when V = V G DD

50. Logic Values as Voltage Levels Logic Value 1 VOH High Noise Margin VOH – VIH VIH VIL Low Noise Margin VIL - VOL VOL Logic Value 0