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Week #2 Slides. Diving Into Spartan 3. Agenda. Recap 15 Years of Evolution to Virtex Four generations of Spartan Project discussion Questions. Logic Cell. Logic Cell. Logic Cell. Logic Cell. Logic Cell. Logic Cell. Logic Cell. Logic Cell. Logic Cell. Logic Cell. Logic
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Week #2 Slides Diving Into Spartan 3
Agenda • Recap • 15 Years of Evolution to Virtex • Four generations of Spartan • Project discussion • Questions
Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell
First IO Cell Note: having All user pins be I/O was a big DEAL!!!
XC3000 Fabric Array Little black dots Are PIPs
XC4000 IO Cell Note
VIRTEX The Fourth Generation NOTE: VIRTEX Equated with Having hard Fixed blocks Embedded in The fabric
… which brings us to Spartan 3(uh, we did skip a bunch of stuff, but the progression for our needs works out . . .)
Spartan 3 • Xilinx and the industry track silicon technology • XC2000 @1.5 micron • XC3000 @ 1 micron • XC4000 @ 0.8 to 0.35 micron • Virtex @ 0.25 micron, V-II @ 0.18-0.13 micron • Spartan 3 & Virtex 4 @ 90 nm • Virtex 5 @65 nm • Spartan 6 @ 45 nm • Virtex 6 @ 40 nm • Etc.
Spartan Philosophy • Offer a more cost effective solution for higher volume markets • Need to reduce costs to do that • Trim features • Reduce test cost • Sacrifice speed over die size • Cheaper packages • Etc. • Spartan is the overall result
Spartan 3 IO Cell Note
Stuff in Black & Grey Common to SliceL & sliceM Blue stuff in SliceM only
Clock nets Do heavy lifting Different nets In each family FYI
Spartan 3E IO Cell Note
Stack the Flash: Spartan 3AN A Single Chip Solution
Projects Depend • On your knowledge • Your skill level • Your confidence • Your interest • Uh . . .I don’t know any of the above points about you! • Only YOU know where you are at on this continuum • My goal is to get you to where you can design on Xilinx FPGAs, which has a LOT to do with the S/W!
Some Ideas • Interfaces • MIX & MATCH things • Buses and memories • Peripherals & memories • Buses & peripherals • Processors & the above • Systems • Build single function items • Combine two or more items • Invent something new
Ahh, the Good Old Days . . . Basic idea: Create useful, correct standard functions then . . . HOOK ‘EM UP!
Graphic stolen from Doug Smith’s Book cover . . .I’m looking for the CD that was optional
Stolen From Smith Like Old TTL Manual