Week #10 Busses & Transmission Lines

1. Week #10 Busses & Transmission Lines ENG3640 Microcomputer Interfacing

2. Topics • Types of Busses • Synchronous Busses • Asynchronous Busses • Semi-Synchronous Busses • Bus Arbitration • Signals along Busses • Transmission Lines • Reflections & Distortions • How to solve the problem? • Bus Terminations ENG3640 Fall 2012

3. Resources • Huang, Chapter 14, Sections • 14.7 Waveforms of Bus Signals • Microcomputer Interfacing, By Harold Stone, 1982 (Chapter II) • “High Speed Digital System Design”: A Handbook of Interconnect Theory and Design Practices, By S. Hall, G. Hall and J. McCall, John Wiley & Sons, INC. 2000 (Chapters I, II) ENG3640 Fall 2012

4. 1-KB SRAM Port AD Analog to Digital 4-KB EEPROM 68HC812A4 Block Diagram CPU12 Port T Timer Module I/O Ports Port S Serial Communication I/O Ports Busses act as the computer skeleton holding all its other organs (functional modules) together ENG3640 Fall 2012

5. Definitions Definition from “Microcomputer Busses”, by R.M. Cram, (Academic Press, 1991). A bus is a tool designed to interconnect the functional blocks of a microcomputer in a systematic manner. It provides for standardization in mechanical form, electrical specifications, and communication protocols between board-level devices. Can extend definition to include the P as well Processor-specific bus : a bus that is intended for use with only one processor or with members of one family of compatible processors. Ex: MC68HC12 Bus Standardized processor-independent bus : a bus that is intended to promote interchangeability among a class of board-level products based on possibly different processors. Ex: PCI Bus ENG3640 Fall 2012

6. Address CPU Data Read Write Memory I/O Device Address CPU Data Memory I/O Read Write I/O Port Memory I/O Device CPU ­ Bus ­ I/O • CPU needs to talk with I/O devices such as keyboard, mouse, video, network, disk drive, LEDs • Memory­mapped I/O • Devices are mapped to specific memory locations just like RAM • Uses load/store instructions just like accesses to memory • Ported I/O (Isolated I/O) • Special bus line and instructions ENG3640 Fall 2012

7. Several types of Busses …. CPU & Memory ALU & Control Slow Speed High Speed ENG3640 Fall 2012

8. A Functional Classification of Busses 1) Processor-Memory Busses --- short, synchronous, high-speed --- processor-specific; often proprietary e.g. RAMBUS, VESA local bus 2) Input/Output (I/O) Busses and Instrument Busses --- asynchronous or semi-synchronous --- must accommodate a variety of data rates --- open standards are used to maximize market e.g. SCSI, GPIB(IEEE- 488), USB, Firewire 3) Backplane Busses --- often midway in performance between processor-memory busses and I/O/Instrument busses --- standard busses are used to reduce design cost and to reduce the time-to-market e.g. VME, NuBus, PCI Note: The distinctions between these three bus types are oftenblurred. ENG3640 Fall 2012

9. System Interfaces and Modularity ENG3640 Fall 2012

10. Bus Properties • Serialization: • Only one component can send a message at any given time. • There is a total order of messages. • Broadcast: • A Module can send a message to several other components without an extra cost ENG3640 Fall 2012

11. Some Bus Terminology Bus protocol: a set of allowed bus signal transition sequences and required timing constraints. Bus operation / transaction: a data transfer or control transfer operation that takes place using bus signals according to a bus protocol. Bus master: a subsystem connected to the bus that can determine the bus operations. More than one bus master can be present on the same bus, but only one bus master can have control (i.e. be active) at a time. e.g. multiple CPU’s, DMAC, Math Co-processor, DMA Bus slave: a subsystem connected to the bus that responds to bus operations initiated by the currently active bus master e.g. RAM, Peripheral Chips Bus arbitration: the process of determining which one of two or more contending bus masters will be awarded control of the bus (and thereby become the active bus master). Arbiter : a circuit that performs arbitration May not be a separate chip, but included in the CPU

12. Components of a Bus Mechanical Layer determines its cost but has very little direct influence on its electrical performance Electrical characteristics determines bus drivers/receivers, signal strength Mechanical Electrical Protocol determines how the bus is driven and how receiver and transmitter send/receive their data Protocol ENG3640 Fall 2012

13. Bus Drivers & Receivers - To drive the bus, a bus driver is needed. To receive data a bus receiver is needed. - A bus driver and receiver have an enable signal to control its connection to the bus. - The bus driver and bus receiver are often combined to form a bus transceiver. ENG3640 Fall 2012

14. Signal Groups within a Typical Bus 1. Data signals -- encode the data that is passed between the bus master and bus slaves -- number of data signals determines the “bit width” of the system -- parity bits or other error detection and correction bits maybe included with each data word 2. Address signals -- used to identify locations in memory, and registers in peripheral chips 68HC812A4 ? 21 wires, A0 - A20 -- number of address signals determines the maximum size of the memory Note: Some or all of the data and address signals may betime-multiplexed on the same bus lines ENG3640 Fall 2012

15. Signal Groups (con’t) 3. Control signals --- used to co-ordinate bus transactions R/W, strobes, enables --- used to arbitrate among: -- multiple possible bus masters Bus conflict may lead to errors and damage of peripherals if two or more modules attempt to use the bus simultaneously. --- power failure handling --- entry into and exit from test modes 4. Power signals --- typically +5 VDC, +12 VDC, -12 VDC, +3.3 VDC --- optionally -5 VDC ENG3640 Fall 2012

16. Usually a clock Timing Terminology Caution: terminology may vary slightly between vendors. Double check by checking data sheets Set-up time , tsu: the minimum length of time that a signal must be valid at a circuit input before a second triggering signal arrives at a second input. Delay time , tco: the length of time that a circuit requires for its output(s) tobegin to change in response to a triggering signal arriving at a second input. Hold time , tho: the minimum length of time that a signal must be kept valid at a circuit input after a triggering signal has been received at a second input. Timing skew , tskew: the maximum range of times over which a particularsignal transition can occur. -- Due to variations in driver output resistance -- Combinational logic takes a while to stabilize

17. t tsu H tho L H L H L tskew H L H L Timing Diagram Notation Changing valuesStable Value, high or lowChanging values Clean transitions Tristated Stable, driven High impedance

18. Bus CPU Device 1 Device 2 Device 3 Bus Protocols • Protocol refers to the set of rules agreed upon by both the bus master and bus slave • Synchronous bus­ transfers occur in relation to successive edges of a clock • Asynchronous bus­ transfers bear no particular timing relationship • Semi­synchronous bus­ Operations/control initiate asynchronously, but data transfer occurs synchronously ENG3640 Fall 2012

19. Synchronous Bus Protocol • Are among the easiest to implement. Why? • Because the only control signal is a clock oscillator • The rising and falling edges of the clock signify, respectively the beginning and end of the bus cycle. • Not only are synchronous protocols the least complex but also lead to fastest transactions. Provided What? • Provided that the responding devices are fast enough to operate at the bus clock speed. • Examples: ISA Bus (Industry Standard Architecture) ENG3640 Fall 2012

20. Clock stable stable Address Instruction Addr Data Addr decoding delay Master (CPU) RD Master (CPU) CS stable unstable unstable stable Data I-fetch data access time Synchronous Bus Protocol • Transfer occurs in relation to successive edges of the system clock • Example: • Memory address is placed on the address bus within a certain time, relative to the rising edge of the clock • By the trailing edge of this same clock pulse, the address information has had time to stabilize, so the READ line is asserted • Once the chip has been selected, then the memory can place the contents of the specified location on the data bus ENG3640 Fall 2012

21. Asynchronous Bus Protocol • Handshaking signals are used to transfer information from source to destination (fully interlocked). • The protocol is inherently slower than synchronous protocol because of extra propagation delay. • The wide acceptance of the fully interlocked asynchronous protocol is largely due to: • Reliability • General efficiency in dealing with devices that have a broad range of response time. • When is it useful? • Useful for systems where CPU and I/O devices run at different speeds ENG3640 Fall 2012

22. Asynchronous Bus Protocol • No system clock used • Example: • Master puts address and data on the bus and then raises the Master signal • Slave sees master signal, reads the data and then raises the Slave signal • Master sees Slave signal and lowers Master signal • Slave sees Master signal lowered and lowers Slave signal Address I see you got it there's some data Master Slave I’ve got it I see you see I got it Data write read We call this exchange “handshaking” ENG3640 Fall 2012

23. Semi Synchronous Bus Protocol • Combines the advantage of synchronous and asynchronous busses: • It has the speed of the synchronous bus • It has the versatility of an asynchronous bus • It basically uses two control signals • Clock from the Master • Wait signal from the Slave • For fast devices the bus is essentially a synchronous bus controlled by the clock alone • If a device cannot respond in one clock cycle it raises a wait signal and accordingly the master halts • Example: SCSI Bus ENG3640 Fall 2012

24. Semi Synchronous Bus Protocol • If device cannot respond in one clock cycle it raises the WAIT signal & master halts • When the slave can respond it drops WAIT & master accepts the slave response using the timing of the standard synchronous protocol. ENG3640 Fall 2012

25. Synchronous vs. Asynchronous Buses • Compare max. bandwidth for a synchronous bus and an asynchronous bus • Synchronous bus • has clock cycle time of 50 ns • each transmission takes 1 clock cycle • Asynchronous bus (see timing diagram) • requires 40 ns per handshake • Find bandwidth for each bus when performing 4-byte reads from a 200ns memory ENG3640 Fall 2012

26. Comparison: Synchronous Bus • Send address to memory: 50 ns • Read memory: 200 ns • Send data to device: 50ns • Total: 300 ns • Max. bandwidth: 4 bytes/300ns = 13.3 MB/second ENG3640 Fall 2012

27. Asynchronous Handshake Protocol • ReadReq: Indicates a read request by CPU from memory • DataRdy: Indicates that data word is now ready on data lines • Ack: Used to acknowledge the ReadReq or DataRdy signal of the other party ENG3640 Fall 2012

28. Asynchronous Handshake Protocol • Memory sees ReadReq, reads address from data bus, raises Ack • I/O device sees Ack high, releases ReadReq and data lines • Memory sees ReadReq low, drops Ack to acknowledge ReadReq • When memory has data ready, it places data on the data lines and raises DataRdy • I/O devices sees DataRdy, reads data from the bus, signals that it has the data by raising Ack • Memory sees the Ack signal, drops DataRdy, releases datalines • If DataRdy goes low, the I/O device drops Ack to indicate that transmission is over R e a d R e q 1 3 D a t a 4 2 6 2 4 A c k 5 7 D a t a R d y ENG3640 Fall 2012

29. Comparison: Asynchronous Bus • Apparently much slower because each step of the protocol takes 40 ns and memory access 200 ns • Notice that several steps are overlapped with memory access time • Memory receives address at step 1 • steps 2,3,4 can overlap with memory access • Step 1: 40 ns • Step 2,3,4: 3 x 40ns =120ns • Steps 5,6,7: max(3 x 40ns = 120ns, 200ns) • Total time: 40ns+120ns+200ns  360ns • max. bandwidth 4bytes/360ns=11.1MB/second ENG3640 Fall 2012

30. Bus Arbitration • Refers to how the busses are controlled. • Single CPU, Memory, I/O • Multiple CPUs, or One CPU and DMA • Bus Arbitration  when more than one master wants to control the bus simultaneously • Simple technique: Every device connects to the bus request line and the first one there gets it Bus CPU Device 1 Device 2 Device 3 Bus request line ENG3640 Fall 2012

31. Bus Arbitration • What happens if multiple devices want access to the bus? • Scheme A: Device  Bus Request Signal, CPU  Bus Grant, Device  Bus Grant Ack • Problem  Simultaneous Request? • Scheme B: daisy chain the devices ­ devices further down the daisy chain pass the request to the CPU ­ device's priority decreases further down the daisy chain Bus Grant Bus CPU Device 1 Device 2 Device 3 Bus grant ack Bus request line Bus CPU Request Device 1 Device 2 Device 3 Grant ENG3640 Fall 2012

32. Coarsest granularity Finest granularity Sharing a Bus Among Multiple Masters 1. Exclusive Control each bus master retains exclusive control of the bus for several bus transactions. 2. Cycle Stealing bus transactions from different bus masters are interleaved on an ad hoc or strictly round-robin basis. e.g. CPU, DMAC1, DMAC2,CPU 3. Split Transaction (Pipelined Bus) read transactions are split into two transactions: 1) master sends read command & target address 2) slave sends a return packet containing data the bus is available to be used by other masters during the memory access time e.g. RAMBUS, Synchronous DRAMs

33. Split Cycle Protocol • A read is split into two separate transactions: • During the first transaction  bus master transmits an address to the slave and then disconnects from the bus • Other masters use the bus … • Slave initiates the 2nd part of the split cycle by accessing the bus as a master and transmitting data to other party which now responds as a slave. Address MASTER SLAVE Data Mater transmits Address to slave Slave transmits Data to Master Bus Idle ENG3640 Fall 2012

34. -- coarse granularity -- simplicity -- software method -- no special hardware Exclusive Control Cycle Stealing -- fairer sharing of the bus -- requires hard- ware support -- requires hard- ware support on bus and in affected devices -- high-speed buses do not have to wait for slowly responding devices Split Transactions PROS CONS -- bus time may not be shared fairly or efficiently -- however this support is available in most CPU’s

35. Summary: Bus Trade-Offs Option High Performance Low Cost 1) Bus Sharing 2) Data Width 3) Transfer Size 4) Bus Masters 5) Split Transactions? 6) Clocking Separate Data & MultiplexedAddress Busses Data & Address Wider is Faster Narrower is < $ e.g. 32, 64 e.g. 16, 8 Block Transfers Single word using using DMA CPU Multiple masters One master,(requires arbitration) the CPU, no arbit. Yes, to get more pipelining No, too complex Synch. With Asynchronous,matched elements semi-synch. ENG3640 Fall 2012

36. Busses as Transmission Lines

37. Introduction: • Designers of electronic circuits, normally make the simplifying assumption that signal propagation over conductors is instantaneous and that the received signal is a faithful replica of the transmitted signal Is this a valid assumption? • We need to understand how signals propagate on wires and learn the type of distortions that might occur as: • Frequency of operation increases • Wire length increases ENG3640 Fall 2012 37

38. Transmission Line Concept Power Frequency (f) is @ 60 Hz Wavelength (l) is 5 106 m ( Over 3,100 Miles) Power Plant Transmission Line Could be considered as Non-Transmission Line Consumer Home • General transmission line: a closed system in which power is transmitted from a source to a destination • Propagation velocity is the speed with which signals are transmitted through the transmission line in its surrounding medium. ENG3640 Fall 2012

39. PC Transmission Lines Integrated Circuit Stripline T Microstrip PCB substrate Cross section view taken here W Via FR4 Dielectric Cross Section of Above PCB Copper Trace Signal (microstrip) Ground/Power Signal (stripline) T Copper Plane Signal (stripline) Ground/Power Signal (microstrip) W Signal Frequency (f) is approaching 10 GHz Wavelength (l) is 1.5 cm ( 0.6 inches) Stripline Micro-Strip ENG3640 Fall 2012

40. Transmission Line “Definition” A two conductor wire system with the wires in close proximity, providing relative impedance, velocity and closed current return path to the source. Characteristic impedance is the ratio of the voltage and current waves at any one position on the transmission line Propagation velocity is the speed with which signals are transmitted through the transmission line in its surrounding medium. Speed of Light Permitivity ENG3640 Fall 2012

41. Wire Delay Signal Transmission: Signal wave-front moves close to the speed of light (~1ft/ns) Time from source to destination is called the “transit time”. In ICs most wires are short, and the transit times are relatively short compared to the clock period. But, long wires on PCB Busses Global Control signals Clock ENG3640 Fall 2012 41

42. Reflections and Distortion on Busses ENG3640 Fall 2012 42

43. Reflections: Example ENG3640 Fall 2012 43

44. Considering Transmission Line Effects • Question: When are transmission line effects important? • Answer: When the wavelength is comparable to the size of the circuit. ENG3640 Fall 2012 44

45. Introduction: (Facts) • In high-speed circuits, transmission line effects tend to distort signals on paths that are long compared to the wavelength of the signals propagating on the paths. • At 100 MHz, wires only a few centimeters long show nonnegligible transmission line effects. • For 50 to 60 Hz, the effects are unnoticeable in ordinary wiring, but become visible on power transmission lines that run a few hundred kilometers. ENG3640 Fall 2012 45

46. Examples of Transmission Line Structures- I Cables and wires (a) Coax cable (b) Wire over ground (c) Tri-lead wire (d) Twisted pair (two-wire line) Long distance interconnects ENG3640 Fall 2012

47. Speed of Signals along Busses • Transfer time for a high speed signal in a wire is controlled by the movement of electrons • Movement of Electrons? • Slows due to impedance of the wire. • Wires have: • Resistance • Capacitance • Inductance • To reason about wires we create models • Ideal • Lumped R, C • Lumped L, R, or C • ….. ENG3640 Fall 2012 47

48. Resistance of wires • Most real wires have resistance • Depends on • Material • Length • Cross Section • What does it cause? • Delay • Loss (power consumption) ENG3640 Fall 2012 48

49. Capacitance of wires • Causes? • Delay. • Loss. • Attenuation. • Real wires have • Resistance • Capacitance Electric Field i = C dv/dt ENG3640 Fall 2012 49

50. Inductance of Wires • Real wires have • Resistance • Capacitance • Inductance Magnetic Field V = L di/dt • Impact of inductance on supply voltages: • Change in current induces a change in voltage • Longer supply lines have larger L ENG3640 Fall 2012 50