Digital Integrated Circuits A Design Perspective

1. Digital Integrated CircuitsA Design Perspective The Inverter

2. V DD V V in out C L The CMOS Inverter: A First Glance -Nucleus of ICs -Analysis can be extended to study Complex logic gates (NAND/NOR/XOR) Cost (complexity and area) Robustness (static/steady state behavior) Performance (dynamic/transient response) Energy efficiency (power/energy consumption)

3. V DD CMOS Inverter N Well PMOS 2l Contacts Out In Metal 1 Polysilicon NMOS GND

4. Two Inverters Share power and ground Abut cells Connect in Metal

5. V V DD DD R p V out V out R n V V V 0 = = in DD in CMOS InverterFirst-Order DC Analysis VOL = 0 VOH = VDD VM = f(Rn, Rp) • Low and High o/p levels equal • VDD and GND (High Noise Margin) • Ratioless (logic levels do not • depend on device sizes) • Vout is always connected to either • VDD or ground (Low o/p impedance) • therefore, Less sensitive to noise. • High i/p impedance (Fanout-large) • No static power dissipation

6. t = f(R .C ) pHL on L = 0.69 R C on L CMOS Inverter: Transient Response V V DD DD R Charging p V out V out -For building fast gates, keep either CL small or decrease the ON resistance of FET -RON is decreased by Increasing W/L ratio NOTE:RON is not fixed C L C L R n discharging V 0 V V = = in DD in (a) Low-to-high (b) High-to-low

7. Voltage TransferCharacteristic

8. CMOS Inverter Load Characteristics

9. CMOS Inverter VTC res: Resisitive/ON VM

10. 1.8 1.7 1.6 1.5 1.4 (V) 1.3 M V 1.2 1.1 1 0.9 0.8 0 1 10 10 /W W p n Switching Threshold as a function of Transistor Ratio -VM is insensitive to small variations in W/L , ie., VTC remains unaffected -Increasing W of PMOS or NMOS moves VM towards VDD or GND VM=(rVDD)/(1+r)

11. VM=(rVDD)/(1+r) considering VDD is very large VM= VDD/2 when r =1 To move VM upwards, a larger value of r is required, which means making the PMOS wider (stronger). Strengthening the NMOS on the other hand, moves VM closer to GND (W/L)p= (W/L)n X (VDSATn K’n)/ (VDSATpK’p)

12. Changing the inverter threshold can improve the circuit reliability

13. V out V OH V M V in V OL V V IL IH Determining VIH and VIL (Noise Margin) A simplified approach

14. Inverter Gain CLM consider (1+λVout) Find dVout/dVin = g by ignoring some second order terms -high gain in transition region (useful for amplifier applications) ID(VM) is current when Vin=VM previous equation: equating saturation currents of PMOS and NMOS and then differentiating to find dVout/dVin = g ; put VM = Vin

15. # an inverter in 0.25 um technology PMOS to NMOS ratio of 3.4 NMOS transistor minimum size (Wn=0.375 um Ln=0.25 um) (59 uA) VM=1.25 V --Find gain g -- Find Noise Margins (* First find ID(Vin=VM); use k’n = 115 x 10-6 , k’p = 30 x 10-6 ,VDSATn= 0.63 V, VDSATp= 1.0 V, VTn=0.43 V, VTp=0.4 V, λn=0.06, λp= -0.1 ; THEN find ‘g’ and then noise margins) # Simulate an inverter with same parameters and compare the calculated and simulated results

16. calculated values of: VIL= 1.2 V, VIH = 1.3 V, NML=NMH = 1.2 V Inverter Gain simulated VTC and gain in 0.25 um process The actual values of VIL= 1.03 V, VIH = 1.45 V, NML= 1.03 V, NMH = 1.05 V

17. #calculated values of: VIL= 1.2 V, VIH = 1.3 V, NML=NMH = 1.2 V #The actual values of VIL= 1.03 V, VIH = 1.45 V, NML= 1.03 V, NMH = 1.05 V These values are lower than those predicted; for two reasons 1) Gain equation overestimates the gain. From gain plot, the maximum gain (at VM) equals only 17. This reduced gain would yield values for VIL and VIH of 1.17 V and 1.33 V. (operating conditions: velocity saturation ?) 2) The gain expression are useful as first order approximations only.

18. Gain=-1 Supply Voltage (VDD) Scaling • subthreshold operation • Low switching current/slow • Operation (watches) • -sensitive to noise (N don’t scale) *trend is to reduce device dimensions and supply voltage, however, threshold voltage is kept constant Reducing VDD improves gain Gain deteriorates at very low supply voltages

19. Why not opt for low voltage operation when the high gain can be achieved at lower supply voltages ?

20. Why not opt for low voltage operation when the high gain can be achieved at lower supply voltages ? --delay ? --sensitive dc characteristics ? --noise sensitive ? Supply must be at least a couple times φT =kT/q (=25 mV at room temperature), thermal noise becomes an issue in unreliable operation. The only way to get CMOS inverters to operate below 100 mV is to reduce the ambient temperature, or in other words to cool the circuit.

21. 2.5 2 Good PMOS Bad NMOS 1.5 Nominal (V) out Good NMOS Bad PMOS V 1 0.5 0 0 0.5 1 1.5 2 2.5 V (V) in Impact of Process Variations (Robustness) The good device has smaller tox(-3nm), smaller L(-25nm), higher W(+30nm), smaller threshold (-60mV) *Operation of the gate is insensitive to process variations

22. Parasitics affecting delay

23. Parasitics affecting delay M1 and M2 are either in cut-off or in the saturation mode (up to 50% point) of the output transient. gate-drain capacitors: Cgd12 = 2 CGD0W (with CGD0 the overlap capacitance per unit width as used in the SPICE model). [*Miller effect] (non-linear) A multiplication factor Keq is introduced to relate the linearized capacitor to the value of the junction capacitance under zero-bias conditions.

24. [Dally 98]

25. Parasitics affecting delay

26. Problem… Find Keq and Keqsw

28. Solution…

29. Solution…

30. Length, width, Fan-out distance and number *It assumes that all components of the gate capacitance are connected between Vout and GND (or VDD), and ignores the Miller effect on the gate-drain capacitances. Second approximation is that the channel capacitance of the connecting gate is constant over the interval of interest. [10% error]

32. 0.25 um CMOS technology. VDD = 2.5 V. From the layout, derive the transistor sizes, diffusion areas, and perimeters. As an example, we will derive the drain area and perimeter for the NMOS tran- sistor. The drain area is formed by the metal-diffusion contact, which has an area of and the rectangle between contact and gate, which has an area of This results in a total area of AD= The perimeter of the drain area is rather involved and consists of the following components (going counterclockwise): 5 + 4 + 4 + 1 +1= *Notice that the gate side of the drain perimeter is not included, as this is not considered a part of the side-wall Similarly, the drain area and perimeter of the PMOS transistor are found

33. drain area and perimeter of the PMOS transistor Wire capacitance Cw can also be calculated This physical information can be combined with the approximations derived above to come up with an estimation of CL using Table 3-5

37. Assignment-5 (Due date: 22/09/14 Multiply each dimension in the layout by 8 (eight) so that channel length is 2 um now and other dimensions also change. Find the propagation delay at the output of first inverter using SPICE simulation and compare it with the one obtained by finding CL, Req, Keq, etcetra using analytical expressions (as taught in the class).

38. Propagation Delay

39. CMOS Inverter Propagation DelayApproach 1

40. CMOS Inverter Propagation DelayApproach 2

41. Transient Response ? *Cgd that couples i/p to o/p even before transistor is ON *Overshoots result in delay Vin tp = (tpLH+tpHL)/2 Vout tp = 0.69 CL (Reqn+Reqp)/2 tpLH tpHL

42. Delay as a function of VDD optimize/manipulate delay *CLM ignored here VDD>> VTn + VDSATn/2 Delay independent of supply

43. Design for Performance • Keep capacitances small • Increase transistor sizes • watch out for self-loading! • Increase VDD (????) - (oxide breakdown, hot electron effects) - (energy-performance tradeoff)

44. -PMOS wider: Rn=Rp, tpLH=tpHL, symmetrical VTC, Noise margin -Delay can be smaller if PMOS is small (else tpHL degrades) Device Sizing (for fixed load) Cint=SCref Req=Rref /S Self-loading effect: Intrinsic capacitances dominate Slow further improvement in delay *Increasing transistor size -> silicon area increases

45. Optimum NMOS/PMOS ratio tpHL tpLH while widening the PMOS improves the tpLH of the inverter by increasing the charging current, it also degrades the tpHL by cause of a larger parasitic capacitance tp How to derive optimum size ? b = Wp/Wn Fig. 5.18

46. Inverter Sizing

47. Finding Optimal Sizing ratio β • β=(W/L)p / (W/L)n • Assumed that WP = 2WN • same pull-up and pull-down currents • approx. equal resistances RN = RP • approx. equal rise tpLH and fall tpHL delays (symmetrical VTC) • doesn’t imply minimum propagation delay • If symmetry and Noise margins are not important then it is • possible to speed up inverter by reducing PMOS width. • (widening PMOS improves tPLH by increasing charging current, but it • degrades tPHL by causing larger parasitic capacitance) • A transistor ratio is required that optimizes propagation delay • of the inverter

48. Optimal Sizing ratio β ….. In Out 1 2 3 CL1 CL CL1 is the load capacitance of first gate • CL1=(Cdp1 + Cdn1) + (Cgp2 + Cgn2)+ CW • When β=(W/L)p / (W/L)n is applied (all other transistor parameters also scale by the same factor) • Cdp1 ≈ βCdn1 and Cgp2 ≈ βCgn2 • so that CL1= (1+β)(Cdn1 + Cgn2)+ CW • from tp = 0.69 CL (Reqn+Reqp)/2

49. Optimal Sizing ratio β ….. where The optimum value of β is found by setting ∂tp/∂β=0 Eqn. 5.26 If the wiring capacitance dominates, larger values of β should be used. Smaller device sizes yield faster designs at the expense of Symmetry and noise margin

50. Consider again our standard design example. From the values of the equivalent resistances (Table 3.3), we find that a ratio β of 2.4 (= 31 kW / 13 kW) would yield a symmetrical transient response. Eq. (5.26) now predicts that the device ratio for an optimal performance should equal 1.6. These results are verified in Figure 5.18, which plots the simulated propagation delay as a function of the transistor ratio b. The graph clearly illustrates how a changing β trades off between tpLH and tpHL. The optimum point occurs around β = 1.9,