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Designing 8-Bit Subset of MIPS Microprocessor: Implementation Overview

This project involves designing an 8-bit subset of a MIPS microprocessor with a 32-bit instruction encoding and 8 registers. The objective includes implementing an 8-bit counter, instruction set, controller, ALU, register file, and more. Tasks encompass logic design, controller FSM, integration, memory simulation, and layout. Requirements for submission involve standard cells, IC layout, design verification, and optimization considerations.

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Designing 8-Bit Subset of MIPS Microprocessor: Implementation Overview

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  1. Design and Implementation of VLSI Systems (EN0160) Lecture 26: Project Overview Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley – Rabaey/Pearson]

  2. Objective: Design an 8-bit subset of a MIPS microprocessor 32-bit instruction encoding 8 registers $0-$7 (Register $0 is hardwired to be 0) An 8-bit counter (PC) 10 instructions Project Overview

  3. MIPS instruction set

  4. Instruction format

  5. Example program (required testbench) compile

  6. Example program (required testbench) Translate

  7. MIPS organization

  8. Controller generates multiplexer select signals and register enables to sequence the datapath Controller is a FSM that controls the CPU

  9. ALU control

  10. Logic Design Each read/write takes four cycles to read 32 bits from the memory

  11. Block diagram

  12. Main parts 2 2 2 1 2

  13. Controller FSM (2) ALU (2) Register file (2) ALU control (1) Integration/Memory/simulating the program (2) Main tasks

  14. Timeline

  15. Requirements for each design you submit • Please include all the following when you submit to the integrator. • Standard cells (verified w power/area/timing numbers) (2 points) • Prototype IC layout included (6 points) • Include functional design verification (7 points) • Describe how did you optimize/constrain your design in terms of area/time/power/reliability (5 points)?

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